MSP430F6776IPZ datasheet(74/157 Pages) TI

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SU,MI

HD,MI

UCLK

SOMI

SIMO

VALID,MO

CKPL =0

CKPL =1

LOW/HIGH

1/f

UCxCLK

STE

STE,LEAD

STE,LAG

STE,ACC

STE,DIS

UCMODEx=01

UCMODEx=10

ECCN 5E002 TSPA - Technology / Software Publicly Available

MSP430F677x

MSP430F676x

MSP430F674x

SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013

www.ti.com

eUSCI (SPI Master Mode) (continued)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

(1)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

2 V

tHD,MI

SOMI input data hold time

3 V

2 V

UCLK edge to SIMO valid,

tVALID,MO

SIMO output data valid time(2)

CL = 20 pF

3 V

2 V

tHD,MO

SIMO output data hold time(3)

CL = 20 pF

3 V

(2)

Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams

in Figure 12 and Figure 13.

(3)

Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data

on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in

Figure 12 and Figure 13.

Figure 12. SPI Master Mode, CKPH = 0

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