MSP430F6776IPZ datasheet(73/157 Pages) TI

73 / 157 page

ECCN 5E002 TSPA - Technology / Software Publicly Available

MSP430F677x

MSP430F676x

MSP430F674x

www.ti.com

SLAS768C – SEPTEMBER 2012 – REVISED APRIL 2013

Timer_A

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

Internal: SMCLK or ACLK,

fTA

Timer_A input clock frequency

External: TACLK,

1.8 V, 3 V

MHz

Duty cycle = 50% ± 10%

All capture inputs.

tTA,cap

Timer_A capture timing

Minimum pulse duration required for

1.8 V, 3 V

capture.

eUSCI (UART Mode) Recommended Operating Conditions

PARAMETER

CONDITIONS

VCC

MIN

TYP

MAX

UNIT

Internal: SMCLK or ACLK,

feUSCI

eUSCI input clock frequency

External: UCLK,

fSYSTEM

MHz

Duty cycle = 50% ± 10%

BITCLK clock frequency

fBITCLK

MHz

(equals baud rate in MBaud)

eUSCI (UART Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

UCGLITx = 0

UCGLITx = 1

UART receive deglitch time(1)

2 V, 3 V

UCGLITx = 2

150

UCGLITx = 3

120

200

(1)

Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are

correctly recognized, their duration should exceed the maximum specification of the deglitch time.

eUSCI (SPI Master Mode) Recommended Operating Conditions

PARAMETER

CONDITIONS

VCC

MIN

TYP

MAX

UNIT

Internal: SMCLK or ACLK,

feUSCI

eUSCI input clock frequency

fSYSTEM

MHz

Duty cycle = 50% ± 10%

eUSCI (SPI Master Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

(1)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

UCSTEM = 0, UCMODEx = 01 or 10

2 V, 3 V

150

tSTE,LEAD

STE lead time, STE low to clock

UCSTEM = 1, UCMODEx = 01 or 10

2 V, 3 V

150

UCSTEM = 0, UCMODEx = 01 or 10

2 V, 3 V

200

STE lag time, Last clock to STE

tSTE,LAG

high

UCSTEM = 1, UCMODEx = 01 or 10

2 V, 3 V

200

2 V

UCSTEM = 0, UCMODEx = 01 or 10

STE access time, STE low to

tSTE,ACC

SIMO data out

2 V

UCSTEM = 1, UCMODEx = 01 or 10

3 V

2 V

UCSTEM = 0, UCMODEx = 01 or 10

STE disable time, STE high to

tSTE,DIS

SIMO high impedance

2 V

UCSTEM = 1, UCMODEx = 01 or 10

3 V

2 V

tSU,MI

SOMI input data setup time

3 V

(1)

fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave)).

For the slave's parameters tSU,SI(Slave) and tVALID,SO(Slave) see the SPI parameters of the attached slave.

Submit Documentation Feedback

MSP430F6776IPZ bảng dữ liệu(PDF) 73 Page - Texas Instruments

MSP430F6776IPZ bảng dữ liệu(HTML) 73 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL