AMC7812SPAPR datasheet(56/92 Pages) TI

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AMC7812

SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013

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Serial Peripheral Interface (SPI)

The AMC7812 can be controlled over a versatile 3-wire serial interface that operates at clock rates of up to

50MHz and is compatible with SPI, QSPI™, MICROWIRE™, and DSP standards. The SPI communication

command consists of a read/write bit, seven register address bits, and 16 data bits (as shown in Table 9), for a

total of 24 bits. The timing for this operation is shown in the SPI timing diagrams (Figure 3, Figure 4, and

Figure 5).

SPI Shift Register

The SPI shift register is 24 bits wide. Data are loaded into the device MSB first as a 24-bit word under the control

of the serial clock input, SCLK. The falling edge of CS starts the communication cycle. The data are latched into

the SPI shift register on the falling edge of SCLK, while CS is low. When CS is high, the SCLK and SDI signals

are blocked out and the SDO line is in a high-impedance state. The contents of the SPI shift register are loaded

into the device internal register on the rising edge of CS (with delay). During the transfer, the command is

decoded and the new data are transferred into the proper registers.

The serial interface works with both a continuous and non-continuous serial clock. A continuous SCLK source

can only be used if CS is held low for the correct number of clock cycles. In gated clock mode, a burst clock

containing the exact number of clock cycles must be used and CS must be taken high after the final clock to

latch the data.

AMC7812 Communications Command for SPI

The AMC7812 is entirely controlled by registers. Reading from and writing to these registers is accomplished by

issuing a 24-bit operation word shown in Table 9.

Table 9. 24-Bit Word Structure for Read/Write Operation

OPERATION

I/O

BIT 23 (MSB)

BIT22:BIT16

BIT15:BIT0

SDI

0 (R/W)

Addr6:Addr0

Data to be written

Write

Undefined or data depending on the

SDO

Data is undefined

previous frame

SDI

1 (R/W)

Addr6:Addr0

don't care

Read frame 1

Undefined or data depending on the

SDO

Data is undefined

previous frame

SDI

1 (R/W)

Addr6:Addr0

don't care

Read frame 2

SDO

Data is undefined

Data for address specified in frame 1

Bit 23

R/W. Indicates a read from or a write to the addressed register.

Bit = '0' sets the write operation and the data are written to the specified register.

Bit = '1' sets the read operation where bits [addr6:addr0] select the register to be read. The remaining bits are don't care.

The data read from the selected register appear on SDO pin in the next SPI cycle.

Bits[22:16]

Addr6:Addr0. Register address; specifies which register is accessed.

Bits[15:0]

DATA. 16-bit data bits.

In write operation, these bits are written to bits[15:0] of the register with the address of [Addr6:Addr0].

In read operation, these bits are determined by previous operation. If previous operation is a read, these bits are from

bits[15:0] of the internal register specified in previous read operation. If previous operation is a write, these data bits are

don’t care (undefined). The data read from current read operation appears on SDO in the next operation cycle.

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