AMC7812SPAPR datasheet(50/92 Pages) TI

50 / 92 page

AMC7812

SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013

www.ti.com

F/S-Mode Protocol

•

The master initiates the data transfer by generating a start condition. The start condition is when a high-to-low

transition occurs on the SDA line while SCL is high, as shown in Figure 2. All I2C-compatible devices must

recognize a start condition.

•

The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit

R/W on the SDA line. During all transmissions, the master ensures that data are valid. A valid data condition

requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 2). All devices

recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave

device with a matching address generates an acknowledge (see Figure 2) by pulling the SDA line low during

the entire high period of the ninth SCL cycle. Upon detecting this acknowledge, the master recognizes that

communication link with a slave has been established.

•

The master generates further SCL cycles to either transmit data to the slave (R/W bit = '1') or receive data

from the slave (R/W bit = '0'). In either case, the receiver must acknowledge the data sent by the transmitter.

Therefore, an acknowledge signal can either be generated by the master or by the slave, depending on which

one is the receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can

continue as long as necessary.

•

To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low-

to-high while the SCL line is high (see Figure 2). This action releases the bus and stops the communication

link with the addressed slave. All I2C-compatible devices must recognize the stop condition. Upon the receipt

of a stop condition, all devices recognize that the bus is released and wait for a start condition followed by a

matching address.

Hs-Mode Protocol

•

When the bus is idle, both SDA and SCL lines are pulled high by the pull-up devices.

•

The master generates a start condition followed by a valid serial byte containing Hs master code 00001xxx.

This transmission is made in F/S mode at no more than 400 kbps. No device is allowed to acknowledge the

Hs master code, but all devices must recognize it and switch their internal setting to support 3.4 Mbps

operation.

•

The master then generates a repeated start condition (a repeated start condition has the same timing as the

start condition). After this repeated start condition, the protocol is the same as for F/S mode, except that

transmission speeds up to 3.4 Mbps are allowed. A stop condition ends Hs mode and switches all the internal

settings of the slave devices to support F/S mode. Note that instead of using a stop condition, repeated start

conditions should be used to secure the bus in Hs mode.

Address Pointer

The Address Pointer Register of AMC7812 is an 8-bit register. Each register has an address and when it is

accessed, the address pointer points to it. All registers in the AMC7812 are 16-bit, consisting of a high byte

(D15:D8) and a low byte (D7:D0). The high byte is always accessed first, and the low byte accessed second.

When the register is accessed, the entire register is frozen until the operation on the low byte is complete. During

write operation, the new content does not take effect until the low byte is written. In read operation, the whole

The address pointer does not change after the current register is accessed. To change the pointer, the master

issues a slave address byte with the R/W bit low, followed by the Pointer Register byte; no additional data are

required.

Timeout Function

The AMC7812 resets the serial interface if either SCL or SDA are held low for 32.8ms (typical) between a

START and STOP condition. If the AMC7812 is holding the bus low, it will release the bus and wait for a START

condition. To avoid activating the timeout function, it is necessary to maintain a communication speed of at least

1kHz for the SCL operating frequency.

Submit Documentation Feedback

Product Folder Links: AMC7812

AMC7812SPAPR bảng dữ liệu(PDF) 50 Page - Texas Instruments

AMC7812SPAPR bảng dữ liệu(HTML) 50 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

bảng dữ liệu tải về

Link URL