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AMC7812SPAPR bảng dữ liệu(PDF) 52 Page - Texas Instruments

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tên linh kiện AMC7812SPAPR
Giải thích chi tiết về linh kiện  12-Bit Analog Monitoring and Control Solution with Multichannel ADC, DACs, and Temperature Sensors
PDF  92 Pages
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Trang chủ  http://www.ti.com
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AMC7812SPAPR bảng dữ liệu(HTML) 52 Page - Texas Instruments

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From Master to Slave
A = Acknowledge
N = Not Acknowledge
S = START Condition
P = Stop Condition
Sr = Repeated START Condition
From Slave to Master
Register Pointer
(2nd Register Address)
A
High Byte of Data to
2nd Register
A
Low Byte of Data to
2nd Register
A
S
Device
Slave Address
0
A
Register Pointer
(1st Register Address)
A
High Byte of Data to
1st Register
A
A
Low Byte of Data to
1st Register
Register Pointer
(Last Register Address)
A
High Byte of Data to
Last Register
A
Low Byte of Data to
Last Register
A
P
AMC7812
SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013
www.ti.com
Writing Multiple Words to Different Registers (Figure 101)
A complete word must be written to a register (high byte and low byte) for proper operation.
1. The master device asserts a start condition.
2. The master then sends the 7-bit AMC7812 slave address followed by a zero for the direction bit, indicating a
write operation.
3. The AMC7812 asserts an acknowledge signal on SDA.
4. The master sends the first register address.
5. The AMC7812 asserts an acknowledge signal on SDA.
6. The master sends the high byte of the data word to the first register.
7. The AMC7812 asserts an acknowledge signal on SDA.
8. The master sends the low byte of the data word to the first register.
9. The AMC7812 asserts an acknowledge signal on SDA.
10. The master sends a second register address.
11. The AMC7812 asserts an acknowledge signal on SDA.
12. The master then sends the high byte of the data word to the second register.
13. The AMC7812 asserts an acknowledge on SDA.
14. The master sends the low byte of the data word to the second register.
15. The AMC7812 asserts an acknowledge signal on SDA.
16. The master and the AMC7812 repeat steps 4 to 15 until the last data are transferred.
17. The master then asserts a stop condition to end the transaction.
Figure 101. Write to Multiple 16-Bit Registers
52
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