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DP8110 bảng dữ liệu(PDF) 7 Page - Power-One

tên linh kiện DP8110
Giải thích chi tiết về linh kiện  8V to 14V Input, 0.7V to 5.5V Output
PDF  34 Pages
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DP8110 bảng dữ liệu(HTML) 7 Page - Power-One

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DP8110 10A DC-DC Intelligent dPOL Data Sheet
8V to 14V Input •••• 0.7V to 5.5V Output
BCD.00262 Rev. 1.0, 12 FEB 2013
www.power-one.com
Page 7 of 34
4.5
Signal Specifications
Parameter
Conditions/Description
Min
Nom
Max
Units
VDD
Internal supply voltage
3.15
3.3
3.45
V
Logic In Max
Pull Up Logic max safe input
VDD+.5
V
SYNC/DATA Line (SD pin)
ViL_sd
LOW level input voltage
-0.5
0.3 x VDD
V
ViH_sd
HIGH level input voltage
0.75 x
VDD
VDD + 0.5
V
Vhyst_sd
Hysteresis of input Schmitt trigger
0.25 x
VDD
0.45 x
VDD
V
VoL
LOW level sink current @ 0.5V
14
60
mA
Tr_sd
Maximum allowed rise time 10/90%VDD
300
ns
Cnode_sd
Added node capacitance
5
10
pF
Ipu_sd
Pull-up current source at Vsd=0V
0.3
1.0
mA
Freq_sd
Clock frequency of external SD line
475
525
kHz
Tsynq
Sync pulse duration
22
28
% of clock
cycle
T0
Data=0 pulse duration
72
78
% of clock
cycle
Inputs: ADDR0…ADDR4, EN, IM
ViL_x
LOW level input voltage
-0.5
0.3 x VDD
V
ViH_x
HIGH level input voltage
0.7 x VDD
VDD+0.5
V
Vhyst_x
Hysteresis of input Schmitt trigger
0.1 x VDD
0.3 x VDD
V
RdnL_ADDR
External pull down resistance
ADDRX forced low
10
kOhm
Power Good and OK Inputs/Outputs
Iup_PG
Pull-up current source input forced low PG
25
110
µ
A
Iup_OK
Pull-up current source input forced low OK
175
725
µ
A
ViL_x
LOW level input voltage
-0.5
0.3 x VDD
V
ViH_x
HIGH level input voltage
0.7 x VDD
VDD+0.5
V
Vhyst_x
Hysteresis of input Schmitt trigger
0.1 x VDD
0.3 x VDD
V
IoL
LOW level sink current at 0.5V
4
20
mA
Current Share Bus (CS pin)
Iup_CS
Pull-up current source at VCS = 0V
0.84
3.1
mA
ViL_CS
LOW level input voltage
-0.5
0.3 x VDD
V
ViH_CS
HIGH level input voltage
0.75 x
VDD
VDD+0.5
V
Vhyst_CS
Hysteresis of input Schmitt trigger
0.25 x
VDD
0.45 x
VDD
V
IoL
LOW level sink current at 0.5V
14
60
mA
Tr_CS
Maximum allowed rise time 10/90% VDD
100
ns



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