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PD70F3555 bảng dữ liệu(PDF) 75 Page - Renesas Technology Corp

tên linh kiện PD70F3555
Giải thích chi tiết về linh kiện  32-bit Single-Chip Microcontroller
PDF  88 Pages
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nhà sản xuất  RENESAS [Renesas Technology Corp]
Trang chủ  http://www.renesas.com
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PD70F3555 bảng dữ liệu(HTML) 75 Page - Renesas Technology Corp

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R01DS0141ED0100
Data Sheet
Chapter 7
Peripherals specification
7.17.7
Equivalent circuit
Caution
These specifications are not tested in outgoing inspection. Therefore RIN and
CIN values are not guaranteed and are reference values only.
Additionally these values are specified as maximum values.
7.17.8
ADTRG timing
Notes
1.
n: Number of macro instances. Refer to the User Manual for the detailed
specification.
2.
m: Number of channels. Refer to the User Manual for the detailed
specification.
R
IN
C
IN
ADCAnIm
(n=0, m=0-23)
(n=1, m=0-23)
R
IN
C
IN
ADCAnIm
(n=0, m=0-23)
(n=1, m=0-23)
Terminals
Condition
RIN[kΩ]
CIN[pF]
ADCA0I0-ADCA0I5
When S&H is used
0.7
3.6
When S&H is not
used
ADA0BPC=0
1.6
12.6
ADA0BPC=1
1.5
7.1
ADCA0I6-ADCA0I23
ADA0BPC=0
1.2
11.9
ADA0BPC=1
1.1
7.1
ADCA1I0-ADCA1I23
ADA0BPC=0
1.2
11.9
ADA0BPC=1
1.1
7.1
Parameter
Symbol
Condition
Ratings
Unit
Min
Typ
Max
ADCAnTRGm input High level width
tWADH
with digital noise filter
a
a)
2, 3, 4 or 5 x Tsamp + 20 (Tsamp shows sampling period specified in noise filter).
More than 1 PCLK width of ADC macro must be kept regarding DNF pass through pulse width.
--
ns
without digital noise filter
b
b)
1 × tSYNC+20 ( tSYNC: 1 PCLK of ADC macro)
--
ns
ADCAnTRGm input Low level width
tWADL
with digital noise filter
a
--
ns
without digital noise filter
b
--
ns



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