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PD70F3555 bảng dữ liệu(PDF) 57 Page - Renesas Technology Corp

tên linh kiện PD70F3555
Giải thích chi tiết về linh kiện  32-bit Single-Chip Microcontroller
PDF  88 Pages
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nhà sản xuất  RENESAS [Renesas Technology Corp]
Trang chủ  http://www.renesas.com
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PD70F3555 bảng dữ liệu(HTML) 57 Page - Renesas Technology Corp

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R01DS0141ED0100
Data Sheet
Chapter 7
Peripherals specification
7.8.2
Slave mode
(1)
CSIG timing slave mode
Table 7-5
CSIG timing (Slave mode)
Note
n: Number of macro instances. Refer to the User Manual for the detailed
specification.
(2)
CSIH timing slave mode
Table 7-6
CSIH timing (Slave mode)
Note
n: Number of macro instances. Refer to the User Manual for the detailed
specification.
Parameter
Symbol
Condition
Ratings
Unit
Min
Typ
Max
Macro Operation clock cycle
time
tKCYGn
20.820.83
-
-
ns
CSIGnSC cycle time
tKCYSGn
200
-
-
ns
CSIGnSC high level width
tKWHSGn
0.5 · tKCYSGn-10
-
-
ns
CSIGnSC low level width
tKWLSGn
0.5 · tKCYSGn-10
-
-
ns
CSIGnSI setup time
(vs. CSIGnSC )
tSSISGn
20
-
-
ns
CSIGnSI hold time
(vs. CSIGnSC)
tHSISGn
tKCYGn+5.0
-
-
ns
SO output delay (vs SCKI)
tDSOSGn
-
-
35
ns
CSIGnRYO output delay
tSRYOGn
-
-
35
ns
_CSIGnSSI setup time (vs
CSIGnSC)
tSSSISGn
0.5 · tKCYSn-5.0
-
-
ns
_CSIGnSSI hold time (vs
CSIGnSC)
tHSSISGn
tKCY+5.0
-
-
ns
Parameter
Symbol
Condition
Ratings
Unit
Min
Typ
Max
Macro Operation clock cycle
time
tKCYHn
20.8
-
-
ns
CSIHnSC cycle time
tKCYSHn
200
-
-
ns
CSIHnSC high level width
tKWHSHn
0.5 · tKCYSHn-10
-
-
ns
CSIHnSC low level width
tKWLSHn
0.5 · tKCYSHn-10
-
-
ns
CSIHnSI setup time
(vs. CSIHnSC )
tSSISHn
20
-
-
ns
CSIHnSI hold time
(vs. CSIHnSC)
tHSISHn
tKCYHn+5.0
-
-
ns
SO output delay (vs SCKI)
tDSOSHn
-
-
35
ns
CSIHnRYO output delay
tSRYOHn
-
-
35
ns
CSIHnSSI setup time
(vs. CSIHnSC)
tSSSISHn
0.5 · tKCYSn-5:0
-
-
ns
CSIHnSSI hold time
(vs. CSIHnSC)
tHSSISHn
tKCYn* 5.0
-
-
ns



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