JS28F256P30B95A datasheet(41/97 Pages) MICRON

41 / 97 page

August 2008

Datasheet

Order Number: 306666-12

P30

Note:

Always clear the Status Register prior to resuming erase operations. It avoids Status Register

ambiguity when issuing commands during Erase Suspend. If a command sequence error

occurs during an erase-suspend state, the Status Register contains the command sequence

error status (SR[7,5,4] set). When the erase operation resumes and finishes, possible errors

during the erase operation cannot be detected via the Status Register because it contains the

previous error status.

11.1.1

Clear Status Register

The Clear Status Register command clears the status register. It functions independent

of VPP. The Write State Machine (WSM) sets and clears SR[7,6,2], but it sets bits

SR[5:3,1] without clearing them. The Status Register should be cleared before starting

a command sequence to avoid any ambiguity. A device reset also clears the Status

11.2

Read Configuration Register

The Read Configuration Register (RCR) is used to select the read mode (synchronous or

asynchronous), and it defines the synchronous burst characteristics of the device. To

modify RCR settings, use the Configure Read Configuration Register command (see

Section 6.0, “Command Set” on page 24).

RCR contents can be examined using the Read Device Identifier command, and then

reading from offset 0x05 (see Section 12.0, “Power and Reset Specifications” on

page 50).

The RCR is shown in Table 19. The following sections describe each RCR bit.

Program Suspend Status (PSS)

0 = Program suspend not in effect.

1 = Program suspend in effect.

Block-Locked Status (BLS)

0 = Block not locked during program or erase.

1 = Block locked during program or erase; operation aborted.

0BEFP Status (BWS)

After Buffered Enhanced Factory Programming (BEFP) data is loaded into the

buffer:

0 = BEFP complete.

1 = BEFP in-progress.

Table 18: Status Register Description (Sheet 2 of 2)

Status Register (SR)

Default Value = 0x80

Table 19: Read Configuration Register Description (Sheet 1 of 2)

Read Configuration Register (RCR)

Read

Mode

RES

Latency Count

WAIT

Polarity

Data

Hold

WAIT

Delay

Burst

Seq

CLK

Edge

RES

Burst

Wrap

Burst Length

LC[2:0]

BL[2:0]

Bit

Name

Description

Read Mode (RM)

0 = Synchronous burst-mode read

1 = Asynchronous page-mode read (default)

Reserved (R)

Reserved bits should be cleared (0)

JS28F256P30B95A bảng dữ liệu(PDF) 41 Page - Micron Technology

JS28F256P30B95A bảng dữ liệu(HTML) 41 Page - Micron Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97

bảng dữ liệu tải về

Link URL