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DP83848JSQ bảng dữ liệu(PDF) 51 Page - Texas Instruments

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7.2.2 False Carrier Sense Counter Register (FCSCR)
This counter provides information required to implement the “False Carriers” attribute within the MAU managed object
class of Clause 30 of the IEEE 802.3u specification.
7.2.3 Receiver Error Counter Register (RECR)
This counter provides information required to implement the “Symbol Error During Carrier” attribute within the PHY man-
aged object class of Clause 30 of the IEEE 802.3u specification.
Table 22. False Carrier Sense Counter Register (FCSCR), address 0x14
Bit
Bit Name
Default
Description
15:8
RESERVED
0, RO
RESERVED: Writes ignored, Read as 0
7:0
FCSCNT[7:0]
0, RO / COR
False Carrier Event Counter:
This 8-bit counter increments on every false carrier event. This
counter sticks when it reaches its max count (FFh).
Table 23. Receiver Error Counter Register (RECR), address 0x15
Bit
Bit Name
Default
Description
15:8
RESERVED
0, RO
RESERVED: Writes ignored, Read as 0
7:0
RXERCNT[7:0]
0, RO / COR
RX_ER Counter:
When a valid carrier is present and there is at least one occurrence
of an invalid data symbol, this 8-bit counter increments for each re-
ceive error detected. This event can increment only once per valid
carrier event. If a collision is present, the attribute will not incre-
ment. The counter sticks when it reaches its max count.



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