MPC875CVR133 datasheet(69/84 Pages) FREESCALE

69 / 84 page

MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4

Freescale Semiconductor

FEC Electrical Characteristics

Figure 66 shows the MII transmit signal timing diagram.

Figure 66. MII Transmit Signal Timing Diagram

15.3

MII Async Inputs Signal Timing (MII_CRS, MII_COL)

Table 33 provides information on the MII async inputs signal timing.

Figure 67 shows the MII asynchronous inputs signal timing diagram.

Figure 67. MII Async Inputs Timing Diagram

15.4

MII Serial Management Channel Timing (MII_MDIO, MII_MDC)

Table 34 provides information on the MII serial management channel signal timing. The FEC functions

correctly with a maximum MDC frequency in excess of 2.5 MHz.

Table 33. MII Async Inputs Signal Timing

Num

Characteristic

Min

Max

Unit

MII_CRS, MII_COL minimum pulse width

1.5

—

MII_TX_CLK period

Table 34. MII Serial Management Channel Timing

Num

Characteristic

Min

Max

Unit

M10

MII_MDC falling edge to MII_MDIO output invalid (minimum propagation

delay)

0—

M11

MII_MDC falling edge to MII_MDIO output valid (max prop delay)

—

M12

MII_MDIO (input) to MII_MDC rising edge setup

—

M13

MII_MDIO (input) to MII_MDC rising edge hold

—

M14

MII_MDC pulse width high

40%

60%

MII_MDC period

M15

MII_MDC pulse width low

40%

60%

MII_MDC period

MII_TX_CLK (Input)

MII_TXD[3:0] (Outputs)

MII_TX_EN

MII_TX_ER

MII_CRS, MII_COL

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