MPC875CVR133 datasheet(68/84 Pages) FREESCALE

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MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4

Freescale Semiconductor

FEC Electrical Characteristics

Figure 65 shows MII receive signal timing.

Figure 65. MII Receive Signal Timing Diagram

15.2

MII and Reduced MII Transmit Signal Timing

The transmitter functions correctly up to a MII_TX_CLK maximum frequency of 25 MHz + 1%. There is

no minimum frequency requirement. In addition, the processor clock frequency must exceed the

MII_TX_CLK frequency – 1%.

Table 32 provides information on the MII transmit signal timing.

Table 32. MII Transmit Signal Timing

Num

Characteristic

Min

Max

Unit

MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER invalid

—

MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid

—

MII_TX_CLK pulse width high

35%

65%

MII_TX_CLK period

MII_TX_CLK pulse width low

35%

65%

MII_TX_CLK period

M20_RMII RMII_TXD[1:0], RMII_TX_EN to RMII_REFCLK setup

—

M21_RMII RMII_TXD[1:0], RMII_TX_EN data hold from RMII_REFCLK rising

edge

2—

MII_RX_CLK (Input)

MII_RXD[3:0] (Inputs)

MII_RX_DV

MII_RX_ER

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