Z8018010VSC datasheet(44/85 Pages) ZILOG

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Z80180

Microprocessor Unit

PS014004-1106

Architecture

Figure 27. ASCI Block Diagram

ASCI Registers

ASCI Transmit Shift Register 0 (TSR0, TSR1)—When the ASCI Transmit Shift

shifted out to the TxA pin. When transmission is completed, the next byte (if available) is

automatically loaded from TDR into TSR and the next transmission starts. If no data is

available for transmission, TSR IDLEs by outputting a continuous High level. This

ASCI Transmit Data Register 0,1 (TDR0, TDR1)— I/O

address = 06h, 07h. Data written to the ASCI Transmit Data Register is

transferred to the TSR as soon as TSR is empty. Data can be written while TSR is shifting out

the previous byte of data. The ASCI transmitter is double buffered.

ASCI Block Diagram

Internal Address/Data Bus

ASCI Transmit Data Register

Ch 0: TDR0

ASCI Transmit Shift Register*

Ch 0: TSR0

ASCI Receive Data FIFO

Ch 0: RDR0

ASCI Receive Shift Register*

Ch 0: RSR0 (8)

ASCI Control Register A

Ch 0: CNTLA0 (8)

ASCI Control Register B

Ch 0: CNTB0 (8)

ASCI Status Register

Ch 0: STAT0 (8)

ASCI Status FIFO

Ch 0

ASCI Transmit Data Register

Ch 1: TDR1

ASCI Transmit Shift Register*

Ch 1: TSR1

ASCI Receive Data FIFO

Ch 1: RDR1

ASCI Receive Shift Register*

Ch 1: RSR1 (8)

ASCI Control Register A

Ch 1: CNTLA1 (8)

ASCI Control Register B

Ch 1: CNTB1 (8)

ASCI Status Register

Ch 1: STAT1 (8)

ASCI Status FIFO

Ch 1

TXA0

RXA0

RTS0

CTS0

DCD0

TXA1

RXA1

CTS1

ASCI

Control

Baud Rate

Generator 0

Baud Rate

Generator 1

CKA0

CKA1

Note: *Not Program

Interrupt Request

Accessible.

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