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Z8018010VSC bảng dữ liệu(PDF) 21 Page - Zilog, Inc. |
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Z8018010VSC bảng dữ liệu(HTML) 21 Page - Zilog, Inc. |
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21 / 85 page ![]() Z80180 Microprocessor Unit 15 PS014004-1106 Architecture updated, corrupting the transmit operation in progress. Reading TRDR while a transmit or receive is in progress must be avoided. Figure 7. CSIO Block Diagram Operation Modes Z80® versus 64180 Compatibility The Z80180 is descended from two different ancestor processors, ZiLOG's original Z80 and the Hitachi 64180. The Operating Mode Control Register (OMCR), illustrated in Figure 8, can be programmed to select between certain Z80 and 64180 differences. . Figure 8. Operating Control Register (OMCR: I/O Address = 3Eh) M1E (M1 Enable)— This bit controls the M1 output and is set to a 1 during RESET. When M1E = 1, the M1 output is asserted Low during the opcode fetch cycle, the INT0 acknowledge cycle, and the first machine cycle of the NMI acknowledge. Internal Address/Data Bus CSIO Transmit/Receive Data Register: TRDR (8) CSIO Control Register: CNTR (8) Baud Rate Generator TXS RXS CKS φ Interrupt Request D7 Reserved D6 D5 — IOC (R/W) M1TE (W) M1E (R/W) — —— — |
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