Z8018010VSC datasheet(26/85 Pages) ZILOG

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Z80180

Microprocessor Unit

PS014004-1106

Architecture

execution of the SLEEP instruction. In this mode, on-chip I/O and CPU stop operating,

reducing power consumption, but the PHI output continues to operate. Recovery from SYS-

TEM STOP

mode is the same as recovery from SLEEP mode except that internal I/O sources

(disabled by IOSTOP) cannot generate a recovery interrupt.

Standard Test Conditions

The DC Characteristics section applies to the following standard test

conditions, unless otherwise noted. All voltages are referenced to

GND

(0 V). Positive current flows in to the referenced pin.

All AC parameters assume a load capacitance of 100 pF. Add 10 ns delay for each 50 pF

increase in load up to a maximum of 200 pF for the data bus and 100 pF for the address and

control lines. AC timing measurements are referenced to 1.5 volts (except for CLOCK,

which is referenced to the 10% and 90% points). The Ordering Information section lists

temperature ranges and product numbers. Package drawings are in the

Package Information section (see Figure 15).

Figure 15. AC Load Capacitance Parameters

Absolute Maximum Ratings

Permanent LSI damage occurs if maximum ratings listed in Table 5 are exceeded.

Table 5. Absolute Maximum Ratings

Item

Symbol

Value

Unit

Supply Voltage

VCC

–0.3 ~ +7.0

Input Voltage

VIN

–0.3 ~ VCC +0.3

Operating Temperature

Topr

0 ~ 70

°C

+5 V

From Output

100 pF

Under Test

250

µA

2.1k

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