Z8018010VSC datasheet(69/85 Pages) ZILOG

69 / 85 page

Z80180

Microprocessor Unit

PS014004-1106

Architecture

When DE0 = 0 and the DMA interrupt is enabled (DIE0 = 1), a DMA interrupt request is

made to the CPU.

To perform a software WRITE to DE0, DWE0 must be written with 0 during the same register

WRITE

access. Writing DE0 to 0 disables channel 0 DMA. Writing DE0 to 1 enables channel

0 DMA and automatically sets DME (DMA Main Enable) to 1. DE0 is cleared to 0 during

RESET

DWE1: DE1 Bit WRITE Enable (bit 5)—When performing any

software WRITE to DE1, DWE1 must be written with 0 during the same access. DWE1

always reads as 1.

DWE0: DE0 Bit WRITE Enable (bit 4)—When performing any

software WRITE to DE0, DWE0 must be written with 0 during the same access. DWE0

always reads as 1.

DIE1: DMA Interrupt Enable Channel 1 (bit 3)—When DIE0 is set to 1, the

termination channel 1 DMA transfer (indicated when DE1 = 0) causes a CPU interrupt

request to be generated. When DIE0 = 0, the channel 0 DMA termination interrupt is

disabled. DIE0 is cleared to 0 during RESET.

DIE0: DMA Interrupt Enable Channel 0 (bit 2)—When DIE0 is set to 1, the

termination channel 0 of DMA transfer (indicated when DE0 = 0) causes a CPU interrupt

request to be generated. When DIE0 = 0, the channel 0 DMA termination interrupt is dis-

abled. DIE0 is cleared to 0 during RESET.

DME: DMA Main Enable (bit 0)—A DMA operation is only enabled when its DE bit

(DE0 for channel 0, DE1 for channel 1) and the DME bit is set to 1.

When NMI occurs, DME is reset to 0, disabling DMA activity during the NMI interrupt

service routine. To restart DMA, DE– and/or DE1 must be written with a 1 (even if the

contents are already 1). This WRITE automatically sets DME to 1, allowing DMA operations

to continue.

DME

cannot be directly written. It is cleared to 0 by NMI or indirectly set to 1 by

setting DE0 and/or DE1 to 1. DME is cleared to 0 during RESET.

DMA Mode Register (DMODE)

DMODE

is used to set the addressing and transfer mode for channel 0.

Note:

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