AD9789BBCZ datasheet(62/76 Pages) AD

62 / 76 page

AD9789

Rev. A | Page 62 of 76

RECOMMENDED START-UP SEQUENCE

The steps necessary to optimize the performance of the part and generate an output waveform are listed in Table 79.

Table 79. Recommended System Start-Up Sequence

Step

Description

Data

Power up the AD9789.

Apply the clock.

Enable the clock receiver and set the clock CML.

0x32

0x9E

Enable duty cycle correction.

0x30

0x80

0x24

0x00

Enable digital clocks.

0x24

0x80

0x2F

0xCE

0x33

0x42

0x39

0x4E

Set up mu controller.

0x3A

0x6C

Disable all interrupts.

0x03

0x00

Clear all interrupts.

0x04

0xFE

Enable mu control interrupts.

0x03

0x0C

Enable mu delay controller.

0x33

0x43

Set up digital datapath.

0x06 to 0x15

Set up rate converter.

0x16 to 0x1B

Set up BPF center frequency.

0x1C to 0x1D

Set up interface.

0x20 to 0x23

Set up channel gains.

0x25 to 0x28

Set up spectral invert.

0x29

Set up full-scale current.

0x3C to 0x3D

Wait until mu delay controller is locked (SPI read)1.

0x04

0x08

Update rate converter and BPF.

0x1E

0x80

0x24

0x00

Update interface clocks.

0x24

0x80

Enable channels.

0x05

Enable other interrupts if desired.

0x03

1 Typical lock time of the mu controller is approximately 180,000 DAC cycles (at 2 GSPS, ~75 μs).

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