DSPIC33FJ64GS406 datasheet(260/456 Pages) MICROCHIP

260 / 456 page

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

DS70591E-page 260

 2009-2012 Microchip Technology Inc.

DFLTxCON: DIGITAL FILTER x CONTROL REGISTER

U-0

R/W-0

—

—IMV<2:0>

CEID

bit 15

bit 8

R/W-0

U-0

QEOUT

QECK<2:0>

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-11

Unimplemented: Read as ‘0’

bit 10-9

IMV<1:0>: Index Match Value bits – These bits allow the user application to specify the state of the

QEAx and QEBx input pins during an Index pulse when the POSxCNT register is to be reset.

In x4 Quadrature Count Mode:

IMV1 = Required state of Phase B input signal for match on index pulse

IMV0 = Required state of Phase A input signal for match on index pulse

In x4 Quadrature Count Mode:

IMV1 = Selects phase input signal for index state match (0 = Phase A, 1 = Phase B)

IMV0 = Required state of the selected phase input signal for match on index pulse

bit 8

CEID: Count Error Interrupt Disable bit

1 = Interrupts due to count errors are disabled

0 = Interrupts due to count errors are enabled

bit 7

QEOUT: QEAx/QEBx/INDXx Pin Digital Filter Output Enable bit

1 = Digital filter outputs are enabled

0 = Digital filter outputs are disabled (normal pin operation)

bit 6-4

QECK<2:0>: QEAx/QEBx/INDXx Digital Filter Clock Divide Select Bits

111 = 1:256 clock divide

110 = 1:128 clock divide

101 = 1:64 clock divide

100 = 1:32 clock divide

011 = 1:16 clock divide

010 = 1:4 clock divide

001 = 1:2 clock divide

000 = 1:1 clock divide

bit 3-0

Unimplemented: Read as ‘0’

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