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dsPIC33FJ64GS406 bảng dữ liệu(PDF) 258 Page - Microchip Technology |
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dsPIC33FJ64GS406 bảng dữ liệu(HTML) 258 Page - Microchip Technology |
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258 / 456 page ![]() dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 DS70591E-page 258 2009-2012 Microchip Technology Inc. REGISTER 17-1: QEIxCON: QEIx CONTROL REGISTER (x = 1 or 2) R/W-0 U-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 CNTERR(1) — QEISIDL INDEX UPDN(2) QEIM<2:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SWPAB PCDOUT TQGATE TQCKPS<1:0>(3) POSRES(4) TQCS UPDN_SRC(5) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CNTERR: Count Error Status Flag bit(1) 1 = Position count error has occurred 0 = No position count error has occurred bit 14 Unimplemented: Read as ‘0’ bit 13 QEISIDL: QEIx Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12 INDEX: Index Pin State Status bit (read-only) 1 = Index pin is high 0 = Index pin is low bit 11 UPDN: Position Counter Direction Status bit(2) 1 = Position counter direction is positive (+) 0 = Position counter direction is negative (-) bit 10-8 QEIM<2:0>: Quadrature Encoder Interface Mode Select bits 111 = Quadrature Encoder Interface is enabled (x4 mode) with the position counter reset by the match (MAXxCNT) 110 = Quadrature Encoder Interface is enabled (x4 mode) with the Index Pulse Reset of the position counter 101 = Quadrature Encoder Interface is enabled (x2 mode) with the position counter reset by the match (MAXxCNT) 100 = Quadrature Encoder Interface is enabled (x2 mode) with the Index Pulse Reset of the position counter 011 = Unused (module disabled) 010 = Unused (module disabled) 001 = Starts 16-bit timer 000 = Quadrature Encoder Interface/timer off bit 7 SWPAB: Phase A and Phase B Input Swap Select bit 1 = Phase A and Phase B inputs are swapped 0 = Phase A and Phase B inputs are not swapped bit 6 PCDOUT: Position Counter Direction State Output Enable bit 1 = Position counter direction status output is enabled (QEI logic controls state of I/O pin) 0 = Position counter direction status output is disabled (normal I/O pin operation) Note 1: CNTERR flag only applies when QEIM<2:0> = 110 or 100. 2: Read-only bit when QEIM<2:0> = 1xx. Read/write bit when QEIM<2:0> = 001. 3: Prescaler utilized for 16-Bit Timer mode only. 4: This bit applies only when QEIM<2:0> = 100 or 110. 5: When configured for QEI mode, this control bit is a ‘don’t care’. |
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