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JS28F128P33TF70A bảng dữ liệu(PDF) 32 Page - Microchip Technology

tên linh kiện JS28F128P33TF70A
Giải thích chi tiết về linh kiện  128-Mbit, 64-Mbit Single Bit per Cell (SBC)
PDF  88 Pages
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nhà sản xuất  MICROCHIP [Microchip Technology]
Trang chủ  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

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P33-65nm
Datasheet
Jul 2011
32
Order Number: 208034-04
11.0
Status Register
To read the Status Register, issue the Read Status Register command at any address.
Status Register information is available to which the Read Status Register, Word
Program, or Block Erase command was issued. SRD is automatically made available
following a Word Program, Block Erase, or Block Lock command sequence. Reads from
the device after any of these command sequences outputs the device’s status until
another valid command is written (e.g. the Read Array command).
The Status Register is read using single asynchronous-mode or synchronous burst
mode reads. SRD is output on DQ[7:0], while 0x00 is output on DQ[15:8]. In
asynchronous mode the falling edge of OE#, or CE# (whichever occurs first) updates
and latches the Status Register contents. However, when reading the Status Register in
synchronous burst mode, CE# or ADV# must be toggled to update SRD.
The Device Ready Status bit (SR.7) provides overall status of the device. SR[6:1]
present status and error information about the program, erase, suspend, VPP, and
block-locked operations.
Table 11: Status Register Description
Status Register (SR)
Default Value = 0x80
Device Ready
Status
Erase
Suspend
Status 1
1. Always clear the Status Register before resuming erase operations afer an Erase Suspend command; this prevents ambiguity in
Status Register information. For example, if a command sequence error occurs during an erase suspend state, the Status
Register contains the command sequence error status (SR[7,5,4] set). When the erase operation resumes and finishes, possible
errors during the erase operation cannot be deteted via the Stauts Register because it contains the previous error status.
Erase/Blank
Check Status
Program
Status
VPP Status
Program
Suspend
Status
Block-Locked
Status
BEFP Write
Status
DRS
ESS
ES
PS
VPPS
PSS
BLS
BWS
765
43210
Bit
Name
Description
7
Device Ready Status
0 = Device is busy; program or erase cycle in progress; SR.0 valid.
1 = Device is ready; SR[6:1] are valid.
6
Erase Suspend Status
0 = Erase suspend not in effect.
1 = Erase suspend in effect.
5
Erase/Blank
Check Status
Command
Sequence
Error
SR.5
SR.4
Description
4
Program
Status
0
0
1
1
0
1
0
1
Program or Erase operation successful.
Program error -operation aborted.
Erase or Blank Check error - operation aborted.
Command sequence error - command aborted.
3
VPP Status
0 = VPP within acceptable limits during program or erase operation.
1 = VPP < VPPLK during program or erase operation.
2
Program Suspend Status
0 = Program suspend not in effect.
1 = Program suspend in effect.
1Block-Locked Status
0 = Block not locked during program or erase.
1 = Block locked during program or erase; operation aborted.
0BEFP Write Status 2
2. BEFP mode is only valid in array.
After Buffered Enhanced Factory Programming (BEFP) data is loaded into the
buffer:
0 = BEFP complete.
1 = BEFP in-progress.



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