WM8953ECSSLASHRV datasheet(71/100 Pages) WOLFSON

71 / 100 page

Production Data

WM8953

PD, January 2009, Rev 4.0

BCLK CONTROL

In Master Mode, BCLK is derived from SYSCLK via a programmable division set by BCLK_DIV, as

described in Table 41. BCLK_DIV must be set to an appropriate value to ensure that there are

sufficient BCLK cycles to transfer the complete data words from the ADCs.

In Slave Mode, BCLK is generated externally and appears as an input to the ADC. The host device

must provide sufficient BCLK cycles to transfer complete data words from the ADCs.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R6 (06h)

4:1

BCLK_DIV

[3:0]

0100b

BCLK Frequency (Master Mode)

0000 = SYSCLK

0001 = SYSCLK / 1.5

0010 = SYSCLK / 2

0011 = SYSCLK / 3

0100 = SYSCLK / 4

0101 = SYSCLK / 5.5

0110 = SYSCLK / 6

0111 = SYSCLK / 8

1000 = SYSCLK / 11

1001 = SYSCLK / 12

1010 = SYSCLK / 16

1011 = SYSCLK / 22

1100 = SYSCLK / 24

1101 = SYSCLK / 32

1110 = SYSCLK / 44

1111 = SYSCL:K / 48

Table 41 BCLK Control

OPCLK CONTROL

A clock output (OPCLK) derived from SYSCLK may be output via GPIO3, GPIO4 or GPIO5. This

clock is enabled by register bit OPCLK_ENA, and its frequency is controlled by OPCLKDIV.

This output of this clock is also dependent upon the GPIO register settings described under “General

Purpose Input/Output”.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R6 (06h)

12:9

OPCLKDIV

[3:0]

0000b

GPIO Output Clock Divider

0000 = SYSCLK

0001 = SYSCLK / 2

0010 = SYSCLK / 3

0011 = SYSCLK / 4

0100 = SYSCLK / 5.5

0101 = SYSCLK / 6

0110 = SYSCLK / 8

0111 = SYSCLK / 12

1000 = SYSCLK / 16

1001 to 1111 = Reserved

R2 (02h)

OPCLK_ENA

(rw)

GPIO Clock Output Enable

0 = disabled

1 = enabled

Table 42 OPCLK Control

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