WM8953ECSSLASHRV datasheet(57/100 Pages) WOLFSON

tên linh kiện	WM8953ECS/RV

Giải thích chi tiết về linh kiện	Low Power Stereo ADC with PLL and TDM Interface

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Production Data

WM8953

PD, January 2009, Rev 4.0

Figure 31 Audio Interface Output Control

The Audio Interface output control is illustrated above. The master mode control register AIF_MSTR

and the left-right clock control register ADCLRC_DIR determine whether the WM8953 generates the

associated clocks. These registers are described in Table 32 below.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

AIF_MSTR

Audio Interface Master Mode Select

0 = Slave mode

1 = Master mode

R8 (08h)

ADCLRC_DIR

ADCLRC Direction

(Forces ADCLRC clock to be output in

slave mode)

0 = ADCLRC normal operation

1 = ADCLRC clock output enabled

Table 32 Audio Interface Output Function Control

OPERATION WITH TDM

Time division multiplexing (TDM) allows multiple devices to transfer data simultaneously on the same

bus. The WM8953 supports TDM in master and slave modes for all data formats and word lengths.

TDM is enabled using register bit AIFADC_TDM. The TDM data slot is programmed using register bit

AIFADC_TDM_CHAN.

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