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WM8953ECS/RV bảng dữ liệu(PDF) 58 Page - Wolfson Microelectronics plc

tên linh kiện WM8953ECS/RV
Giải thích chi tiết về linh kiện  Low Power Stereo ADC with PLL and TDM Interface
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nhà sản xuất  WOLFSON [Wolfson Microelectronics plc]
Trang chủ  http://www.wolfsonmicro.com
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WM8953ECS/RV bảng dữ liệu(HTML) 58 Page - Wolfson Microelectronics plc

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WM8953
Production Data
w
PD, January 2009, Rev 4.0
58
Figure 32 TDM with WM8953 as Master
Figure 33 TDM with Other ADC as Master
Figure 34 TDM with Processor as Master
Note:
The WM8953 is a 24-bit device. If the user operates the WM8953 in 32-bit mode then the 8
LSBs are not driven. It is therefore recommended to add a pull-down resistor if necessary to the
ADCDAT line in TDM mode.
BCLK DIVIDE
The BCLK frequency is controlled by BCLK_DIV. The BCLK frequency must be set appropriately to
support the sample rate of the ADC.
Internal clock divide and phase control mechanisms ensure that the BCLK and ADCLRC edges will
occur in a predictable and repeatable position relative to each other and to the data for a given
combination of ADC sample rate and BCLK_DIV settings.
See “Clocking and Sample Rates” section for more information.



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