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STM32F103RCT6 bảng dữ liệu(PDF) 66 Page - STMicroelectronics

tên linh kiện STM32F103RCT6
Giải thích chi tiết về linh kiện  Clock, reset and supply management
PDF  130 Pages
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STM32F103RCT6 bảng dữ liệu(HTML) 66 Page - STMicroelectronics

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Electrical characteristics
STM32F103xC, STM32F103xD, STM32F103xE
66/130
Doc ID 14611 Rev 8
Figure 26.
Asynchronous multiplexed PSRAM/NOR read waveforms
tv(NADV_NE)
FSMC_NEx low to FSMC_NADV low
5.5
ns
tw(NADV)
FSMC_NADV low time
tHCLK + 1.5
ns
1.
CL = 15 pF.
2.
Based on characterisation, not tested in production.
Table 33.
Asynchronous multiplexed PSRAM/NOR read timings(1)(2)
Symbol
Parameter
Min
Max
Unit
tw(NE)
FSMC_NE low time
7tHCLK – 2
7tHCLK + 2
ns
tv(NOE_NE)
FSMC_NEx low to FSMC_NOE low
3tHCLK – 0.5
3tHCLK + 1.5
ns
tw(NOE)
FSMC_NOE low time
4tHCLK – 1
4tHCLK + 2
ns
th(NE_NOE)
FSMC_NOE high to FSMC_NE high hold time
–1
ns
tv(A_NE)
FSMC_NEx low to FSMC_A valid
0
ns
tv(NADV_NE)
FSMC_NEx low to FSMC_NADV low
3
5
ns
tw(NADV)
FSMC_NADV low time
tHCLK –1.5
tHCLK + 1.5
ns
th(AD_NADV)
FSMC_AD (address) valid hold time after
FSMC_NADV high
tHCLK
ns
th(A_NOE)
Address hold time after FSMC_NOE high
tHCLK
ns
Table 32.
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2)
Symbol
Parameter
Min
Max
Unit
NBL
Data
FSMC_NBL[1:0]
FSMC_AD[15:0]
tv(BL_NE)
th(Data_NE)
Address
FSMC_A[25:16]
tv(A_NE)
FSMC_NWE
t v(A_NE)
ai14892b
Address
FSMC_NADV
t v(NADV_NE)
tw(NADV)
tsu(Data_NE)
th(AD_NADV)
FSMC_NE
FSMC_NOE
tw(NE)
t w(NOE)
tv(NOE_NE)
t h(NE_NOE)
th(A_NOE)
th(BL_NOE)
tsu(Data_NOE)
th(Data_NOE)



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