STM32F102XB datasheet(11/76 Pages) STMICROELECTRONICS

tên linh kiện	STM32F102xB

Giải thích chi tiết về linh kiện	Medium-density USB access line,ARM-based 32b MCU with 64/128KB Flash,USB FS interface,6 timers, ADC&8 com. interfaces

PDF	76 Pages

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nhà sản xuất	STMICROELECTRONICS [STMicroelectronics]

Trang chủ	http://www.st.com

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11 / 76 page

STM32F102x8, STM32F102xB

Description

Doc ID 15056 Rev 4

11/76

Figure 2.

Clock tree

For the USB function to be available, both HSE and PLL must be enabled, with the USB clock output

(USBCLK) at 48 MHz.

To have an ADC conversion time of 1.2 µs, APB2 must be at 12 MHz, 24 MHz or 48 MHz.

The Flash memory programming interface clock (FLITFCLK) is always the HSI clock.

HSE OSC

4-16 MHz

OSC_IN

OSC_OUT

OSC32_IN

OSC32_OUT

LSE OSC

32.768 kHz

LSI RC

40 kHz

HSI RC

8 MHz

to Independent Watchdog (IWDG)

PLL

x2, x3, x4

PLLMUL

Legend:

MCO

Clock Output

Main

PLLXTPRE

..., x16

AHB

Prescaler

/1, 2..512

PLLCLK

HSI

HSE

APB1

Prescaler

/1, 2, 4, 8, 16

ADC

Prescaler

/2, 4, 6, 8

ADCCLK

PCLK1

HCLK

PLLCLK

to AHB bus, core,

memory and DMA

USBCLK

to USB interface

to TIM2, 3

and 4

USB

Prescaler

/1, 1.5

to ADC

LSE

LSI

HSI

/128

HSI

HSE

peripherals

to APB1

Peripheral Clock

Enable (13 bits)

Enable (3 bits)

Peripheral Clock

APB2

Prescaler

/1, 2, 4, 8, 16

PCLK2

peripherals

to APB2

Peripheral Clock

Enable (11 bits)

48 MHz

48 MHz max

48 MHz

48 MHz max

24 MHz max

to RTC

PLLSRC

MCO

CSS

to Cortex System timer

Clock

Enable (3 bits)

SYSCLK

max

RTCCLK

RTCSEL[1:0]

TIMXCLK

IWDGCLK

SYSCLK

FCLK Cortex

free running clock

TIM2,3, 4

If (APB1 prescaler =1) x1

else

HSE = high-speed external clock signal

HSI = high-speed internal clock signal

LSI = low-speed internal clock signal

LSE = low-speed external clock signal

ai14994b

To Flash prog. if FLITFCLK

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