MSC8152 datasheet(56/68 Pages) FREESCALE

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MSC8152 Dual-Core Digital Signal Processor Data Sheet, Rev. 5

Hardware Design Considerations

Freescale Semiconductor

After the above rails rise to 90% of their nominal voltage, the following I/O power rails may rise in any sequence (see

Figure 34): QVDD, NVDD, GVDD1, and GVDD2.

Notes: 1.

If the M3 memory is not used, M3VDD can be tied to GND.

If the MAPLE-B is not used, MVDD can be tied to GND.

If the HSSI port1 is not used, SXCVDD1and SXPVDD1 must be connected to the designated power supplies.

If the HSSI port2 is not used, SXCVDD2 and SXPVDD2 must be connected to the designated power supplies.

If the DDR port 1 interface is not used, it is recommended that GVDD1 be left unconnected.

If the DDR port 2 interface is not used, it is recommended that GVDD2 be left unconnected.

3.1.4

Reset Guidelines

When a debugger is not used, implement the connection scheme shown in Figure 35.

When a debugger is used, implement the connection scheme shown in Figure 36.

Figure 34. Supply Ramp-Up Sequence

Figure 35. Reset Connection in Functional Application

Figure 36. Reset Connection in Debugger Application

VDD, MVDD, M3VDD

90%

NVDD, QVDD, GVDD1, GVDD2

On-board PORESET source

TRST

PORESET

MSC815x

(example: voltage monitor)

ΚΩ

On-board PORESET source

TRST

PORESET

MSC815x

(example: voltage monitor)

On-board TRST source

(example: OnCE)

VDDIO

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