WM8940CGEFLSLASHV datasheet(24/91 Pages) WOLFSON

24 / 91 page

WM8940

Production Data

PD, Rev 4.3, November 2011

Figure 10 ADC Digital Filter Path

The ADC is enabled by the ADCEN register bit.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Power

management 2

ADCEN

0 = ADC disabled

1 = ADC enabled

Table 11 ADC Enable

The polarity of the output signal can also be changed under software control using the ADCPOL

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R14

ADC Control

ADCPOL

0=normal

1=inverted

Table 12 ADC Polarity

SELECTABLE HIGH PASS FILTER

A selectable high pass filter is provided. To disable this filter set HPFEN=0. The filter has two

modes controlled by HPFAPP. In Audio Mode (HPFAPP=0) the filter is first order, with a cut-off

frequency of 3.7Hz. In Application Mode (HPFAPP=1) the filter is second order, with a cut-off

frequency selectable via the HPFCUT register. The cut-off frequencies when HPFAPP=1 are shown

in Table 14.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R14

ADC Control

HPFEN

High Pass Filter Enable

0=disabled

1=enabled

HPFAPP

Select audio mode or application mode

0=Audio mode (1

st order, fc = ~3.7Hz)

1=Application mode (2

nd order, fc =

HPFCUT)

6:4

HPFCUT

000

Application mode cut-off frequency

See Table 14 for details.

Table 13 ADC Filter Select

WM8940CGEFL/V bảng dữ liệu(PDF) 24 Page - Wolfson Microelectronics plc

WM8940CGEFL/V bảng dữ liệu(HTML) 24 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91

bảng dữ liệu tải về

Link URL