WM8940CGEFLSLASHV datasheet(79/91 Pages) WOLFSON

79 / 91 page

Production Data

WM8940

PD, Rev 4.3, November 2011

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

PLL_POWERD

OWN

PLL POWER

0=On

1=Off

Master Clock and

Phase Locked

Loop (PLL)

FRACEN

Fractional Divide within the PLL

0=Disabled (Lower Power)

1=Enabled

Master Clock and

Phase Locked

Loop (PLL)

5:4

PLLPRESCALE 00

00 = MCLK input multiplied by 2 (default)

01 = MCLK input not divided (default)

10 = Divide MCLK by 2 before input to PLL

11 = Divide MCLK by 4 before input to PLL

Master Clock and

Phase Locked

Loop (PLL)

3:0

PLLN[3:0]

1100

Integer (N) part of PLL input/output frequency ratio.

Use values greater than 5 and less than 13.

Master Clock and

Phase Locked

Loop (PLL)

37 (25h)

15:6

000h

Reserved

5:0

PLLK[23:18]

001100

Fractional (K) part of PLL1 input/output frequency ratio

(treat as one 24-digit binary number).

Master Clock and

Phase Locked

Loop (PLL)

38 (26h)

15:9

00h

Reserved

8:0

PLLK[17:9]

010010011

Fractional (K) part of PLL1 input/output frequency ratio

(treat as one 24-digit binary number).

Master Clock and

Phase Locked

Loop (PLL)

39 (27h)

15:9

00h

Reserved

8:0

PLLK[8:0]

011101001

Fractional (K) part of PLL1 input/output frequency ratio

(treat as one 24-digit binary number).

Master Clock and

Phase Locked

Loop (PLL)

40 (28h)

15:0

0000h

Reserved

41 (29h)

15:0

0000h

Reserved

42 (2Ah)

15:2

Reserved

ALCZC

0 (zero

cross off)

ALC uses zero cross detection circuit.

0 = Disabled (recommended)

1 = Enabled

ALC Control 4

Reserved

43 (2Bh)

15:0

0000h

Reserved

44 (2Ch)

15:9

00h

Reserved

MBVSEL

Microphone Bias Voltage Control

0 = 0.9 * AVDD

1 = 0.75 * AVDD

Input Signal Path

7:4

Reserved

AUXMODE

Auxiliary Input Mode

0 = inverting buffer

1 = mixer (on-chip input resistor bypassed)

Input Signal Path

AUX2INPPGA

Select AUX amplifier output as input PGA signal

source.

0=AUX not connected to input PGA

1=AUX connected to input PGA amplifier negative

terminal.

Input Signal Path

MICN2INPPGA 1

Connect MICN to input PGA negative terminal.

0=MICN not connected to input PGA

1=MICN connected to input PGA amplifier negative

terminal.

Input Signal Path

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