ST10F276E datasheet(182/235 Pages) STMICROELECTRONICS

182 / 235 page

Electrical characteristics

ST10F276E

182/235

Doc ID 12303 Rev 3

IALEH

ALE active current(6)(8)

VOUT = 2.4 V

300

µA

IP6H

Port 6 inactive current

(P6[4:0])(6)(7)

VOUT = 2.4 V

-40

µA

IP6L

Port 6 active current (P6[4:0])(6)(8)

VOUT = 0.4V

-500

µA

IP0H

(6)

PORT0 configuration current(6)

VIN = 2.0V

-10

µA

IP0L

(7)

VIN = 0.8V

-100

µA

CIO

Pin capacitance (digital inputs / outputs)

(4)(6)

-10

ICC1

Run mode power supply current(9)

(execution from internal RAM)

20 + 2 fCPU

ICC2

Run mode power supply current(4)(10)

(execution from internal Flash)

20 + 1.8 fCPU mA

IID

Idle mode supply current (11)

20 + 0.6 fCPU mA

IPD1

Power Down supply current (12)

(RTC off, oscillators off, main voltage

regulator off)

TA = 25°C

IPD2

Power Down supply current (12)

(RTC on, main oscillator on, main voltage

regulator off)

TA = 25°C

IPD3

Power down supply current (12)

(RTC on, 32 kHz oscillator on, main voltage

regulator off)

TA = 25°C

1.1

ISB1

Stand-by supply current (12)

(RTC off, Oscillators off, VDD off, VSTBY on)

VSTBY = 5.5V

TA = TJ = 25°C

250

µA

VSTBY = 5.5V

TA = TJ = 125°C

500

µA

ISB2

Stand-by supply current (12)

(RTC on, 32 kHz Oscillator on, main VDD off,

VSTBY on)

VSTBY = 5.5V

TA = 25°C

250

µA

VSTBY = 5.5V

TA = 125°C

500

µA

ISB3

Stand-by supply current (4) (12)

(VDD transient condition)

2.5

This specification is not valid for outputs which are switched to open drain mode. In this case the respective output floats

and the voltage is imposed by the external circuitry.

Port 5 leakage values are granted for not selected A/D converter channel. One channels is always selected (by default,

after reset, P5.0 is selected). For the selected channel the leakage value is similar to that of other port pins.

The leakage of P2.0 is higher than other pins due to the additional logic (pass gates active only in specific test modes)

implemented on input path. Pay attention to not stress P2.0 input pin with negative overload beyond the specified limits:

Failures in Flash reading may occur (sense amplifier perturbation). Refer to Figure 44 for a scheme of the input circuitry.

Not 100% tested, guaranteed by design characterization.

Overload conditions occur if the standard operating conditions are exceeded, that is, the voltage on any pin exceeds the

specified range (that is, VOV > VDD + 0.3V or VOV < -0.3V). The absolute sum of input overload currents on all port pins may

not exceed 50mA. The supply voltage must remain within the specified limits.

Table 90.

DC characteristics (continued)

Symbol

Parameter

Test condition

Limit values

Unit

Min.

Max.

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