ST10F276E datasheet(57/235 Pages) STMICROELECTRONICS

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ST10F276E

Bootstrap loader

Doc ID 12303 Rev 3

57/235

This process may go through several iterations or may directly execute the final application.

In all cases the ST10F276E still runs in BSL mode, that is, with the watchdog timer disabled

and limited access to the internal Flash area. All code fetches from the internal IFLASH area

(01’0000H...08’FFFFH) are redirected to the special Test-Flash. Data read operations

access the internal Flash of the ST10F276E.

5.3.5

Choosing the baud rate for the BSL via UART

The calculation of the serial baud rate for ASC0 from the length of the first zero byte that is

received allows the operation of the bootstrap loader of the ST10F276E with a wide range of

baud rates. However, the upper and lower limits must be kept to ensure proper data transfer.

Equation 1

The ST10F276E uses timer T6 to measure the length of the initial zero byte. The

quantization uncertainty of this measurement implies the first deviation from the real baud

rate; the next deviation is implied by the computation of the S0BRL reload value from the

timer contents. The formula below shows the association:

Equation 2

For a correct data transfer from the host to the ST10F276E, the maximum deviation

between the internal initialized baud rate for ASC0 and the real baud rate of the host should

be below 2.5%. The deviation (FB, in percent) between host baud rate and ST10F276E

baud rate can be calculated using the formula below:

Equation 3

Note:

Function (FB) does not consider the tolerances of oscillators and other devices supporting

the serial communication.

This baud rate deviation is a nonlinear function depending on the CPU clock and the baud

rate of the host. The maxima of the function (FB) increases with the host baud rate due to

the smaller baud rate prescaler factors and the implied higher quantization error (see

Figure 10).

CPU

S0BRL

()

⋅

-------------------------------------------

BST10F276E =

S0BRL

–

--------------------

CPU

Host

---------------

⋅

Contr

Host

–

Contr

----------------------------------------

100

⋅

2.5

≤

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