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ST10F276E bảng dữ liệu(PDF) 115 Page - STMicroelectronics |
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ST10F276E bảng dữ liệu(HTML) 115 Page - STMicroelectronics |
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115 / 235 page ![]() ST10F276E System reset Doc ID 12303 Rev 3 115/235 5 V operation), the asynchronous reset is then immediately entered. 3. RSTIN pin is pulled low if bit BDRSTEN (bit 3 of SYSCON register) was previously set by software. Bit BDRSTEN is cleared after reset. 4. Minimum RSTIN low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked by the internal filter (refer to Section 19.1). Figure 29. Synchronous short / long hardware RESET (EA = 0) 1. RSTIN assertion can be released there. Refer also to Section 19.1 for details on minimum pulse duration. 2. If during the reset condition (RSTIN low), RPD voltage drops below the threshold voltage (about 2.5V for 5V operation), the asynchronous reset is then immediately entered. 3. 3 to 8 TCL depending on clock source selection. 4. RSTIN pin is pulled low if bit BDRSTEN (bit 3 of SYSCON register) was previously set by software. Bit BDRSTEN is cleared after reset. 5. Minimum RSTIN low pulse duration shall also be longer than 500ns to guarantee the pulse is not masked by the internal filter (refer to Section 19.1). |
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