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TNETA1575PGC bảng dữ liệu(PDF) 10 Page - Texas Instruments |
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TNETA1575PGC bảng dữ liệu(HTML) 10 Page - Texas Instruments |
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10 / 45 page ![]() TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 detail description The TNETA1575 device contains the following interfaces: PCI-host interface Cell interface Local-bus interface Control-memory interface Traffic coprocessor interface JTAG interface PCI-host interface The TNETA1575 incorporates a PCI revision 2.1 host interface. The following section describes the features and operation of the PCI-host interface. The TNETA1575 operates as a PCI-slave device for configuration cycles, accesses to internal registers, and accesses to the onboard control memory. It also acts as a PCI-master device for accessing data structures, which are contained in host memory. As a slave, the TNETA1575 incorporates the following features: Directly supports the memory read, memory write, configuration read, and configuration write PCI commands and aliases the memory read multiple, memory read line, and memory write and invalidate to the basic memory commands. Supports single data-cycle transfers and disconnects with retry after the first data cycle. Does not retry single data accesses to any data structures accessed via the SAR, i.e., registers, control memory, or coprocessor. Responds to accesses as a 32-bit agent with medium DEVSEL timing (single wait state) Utilizes a 1-M block of addresses, which is mapped into the host memory space using a single base-address register. Does not support resource locking. As a master, the TNETA1575 incorporates the following features: Utilizes the memory read, memory read line, memory read multiple, and memory write PCI bus commands. Initiates transactions as a 32-bit agent. Performs multiple data-cycle transfers, when possible, up to a maximum of 12 data cycles. The TNETA1575 asserts the IRDY signal one clock cycle after the FRAME signal is asserted. IRDY remains asserted during the burst cycle. |
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