TNETA1575PGC datasheet(5/45 Pages) TI1

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TNETA1575

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH PCI-HOST AND COPROCESSOR INTERFACES

SDNS040C – MAY 1996 – REVISED JUNE 1998

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Terminal Functions (Continued)

PCI-bus interface (continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

SBLENGTH

184

(CMOS)

Sideband length. SBLENGTH indicates to the host when the TNETA1575 is bursting eight free-buffer

entries by asserting SBLENGTH high, or that it is bursting one entry when inactive low. Pulse

duration is for one clock cycle synchronous to the PCI-address phase.

TXQUERDY

185

(CMOS)

Transmit queue ready. TXQUERDY indicates to the host when the transmit queue register is

available for a write access by the host. TXQUERDY is a PCI-sideband signal and is synchronous

with the PCI clock.

cell-segmentation interface

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

Segmentation cell available

SEGCLAV

(CMOS)

PHY mode

SEGCLAV (RXEMPTY/RXCLAV) indicates that a complete cell is available.

(CMOS)

ATM mode

SEGCLAV (TXENB) is active low when SEGDATA contains a valid byte.

Segmentation clock

SEGCLK

(TTL)

PHY mode

SEGCLK (RXCLK) is used to synchronize transfers on SEGDATA. SEGCLK is sourced

from the UTOPIA interface.

(TTL)

ATM mode

SEGCLK (TXCLK) is used to synchronize transfers on SEGDATA. SEGCLK is sourced

from the ATMCLK.

Segmentation data

SEGDATA7–

SEGDATA0

84–87,

89–92

(CMOS)

PHY mode

SEGDATA7–SEGDATA0 (RXDATA) is byte-wide true data that is sourced by the

TNETA1575. SEGDATA7 is the most significant bit.

SEGDATA0

89–92

(CMOS)

ATM mode

SEGDATA7–SEGDATA0 (TXDATA) is byte-wide true data that is sourced by the

TNETA1575. SEGDATA7 is the most significant bit.

Segmentation enable

SEGEN

(TTL)

PHY mode

SEGEN (RXENB) indicates that a valid byte of SEGDATA will be sent during the next

clock cycle.

(TTL)

ATM mode

SEGEN (TXFULL/TXCLAV) indicates that at least one byte of SEGDATA will be

accepted.

Segmentation parity

SEGPAR

(CMOS)

PHY mode

SEGPAR (RXPAR) is the odd-parity bit over SEGDATA7–SEGDATA0.

(CMOS)

ATM mode

SEGPAR (TXPAR) is the odd-parity bit over SEGDATA7–SEGDATA0.

Segmentation start of cell

SEGSOC

(CMOS)

PHY mode

SEGSOC (RXSOC) is active high when SEGDATA contains the first valid byte of the cell

and is sourced by the TNETA1575.

(CMOS)

ATM mode

SEGSOC (TXSOC) is active high when SEGDATA contains the first valid byte of the cell

and is sourced by the TNETA1575.

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