TNETA1575

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH PCI-HOST AND COPROCESSOR INTERFACES

SDNS040C – MAY 1996 – REVISED JUNE 1998

22

POST OFFICE BOX 655303

recommended power-supply sequencing for mixed-voltage devices

The recommended power-supply sequencing in a mixed-voltage system is as follows:

95 percent of their end-point values within a 25-ms time window. All bus contention between the

TNETA1575 and external devices is eliminated by the end of the 25-ms time window. The preferred

order of supply ramping is to ramp the 3.3-V supply, followed by the 5-V supply. This order is not

mandatory, but it allows a larger cumulative number of power-supply on events than does the reverse

order.

values and reach 5 percent of these values within a 25-ms time window. All bus contention between the

TNETA1575 and external devices is eliminated by the end of the 25-ms time window. The preferred

order of supply ramping is to ramp down the 5-V supply, followed by the 3.3-V supply. This order is not

mandatory, but it allows a larger cumulative number of power supply off events than the reverse order.

If these precautions and guidelines are not followed, the TNETA1575 device may experience failures.

timing requirements

PCI-bus interface

NO.

MIN

NOM

MAX

UNIT

fclock(PCLK)

Clock frequency, PCLK†

33

MHz

tsu(BUS)

Setup time, bused signals valid before PCLK

↑ (see Note 6)

7

ns

tsu(PGNT)

Setup time, PGNT low before PCLK

↑ (see Note 6)

10

ns

tsu(PREQ)

Setup time, PREQ low before PCLK

↑ (see Note 6)

12

ns

th(IN)

Hold time, inputs valid after PCLK

↑

0

ns

† The UTOPIA-clock (ATMCLK) frequency cannot be greater than three times the PCI-clock (PCLK) frequency or less than one-third the PCI-clock

(PCLK) frequency because synchronization can break down on the FIFOs and cells can be lost. If this relationship is maintained between the

PCLK clock and the ATMCLK clock, the PCLK clock can operate at or below 33 MHz and cells are not lost.

NOTE 6: PREQ and PGNT are point-to-point signals, and have different output valid delay and input setup times than do bused signals. PGNT

has a setup time of 10 ns; PREQ has a setup time of 12 ns. All other signals are bused.

operating characteristics over recommended operating conditions

PCI-bus interface

NO.

PARAMETER

MIN

MAX

UNIT

td(BUSV)

Delay time, PCLK

↑ to bused signals valid (see Note 6)

2

11

ns

td(PGNT)

Delay time, PCLK

↑ to PGNT low (see Note 6)

2

12

ns

td(PREQ)

Delay time, PCLK

↑ to PREQ low (see Note 6)

2

12

ns

ton(FLT–ACT)

Turn-on time, float to active

2

ns

toff(ACT–FLT)

Turn-off time, active to float

28

ns

ton(RST)

Turn-on time, power stable to reset active

1

ms

ton(PCLK–RST) Turn-on time, PCLK stable to reset active

100

µs

toff(RST–OF)

Turn-off time, reset active to output float

40

ns

NOTE 6. PREQ and PGNT are point-to-point signals, and have different output valid delay and input setup times than do bused signals. PGNT

has a setup time of 10 ns; PREQ has a setup time of 12 ns. All other signals are bused.