TNETA1575

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH PCI-HOST AND COPROCESSOR INTERFACES

SDNS040C – MAY 1996 – REVISED JUNE 1998

35

POST OFFICE BOX 655303

timing requirements (see Note 7 and Figure 18)

UTOPIA interface

NO.

MIN

MAX

UNIT

fclock(ACLK)

Clock frequency, ATMCLK†

0.33 fclock(PCLK)

3 fclock(PCLK)

MHz

1

tw(SEGCLKH)

Pulse duration, SEGCLK high

12

ns

2

tw(SEGCLKL)

Pulse duration, SEGCLK low

12

ns

3

tsu(SEGEN)

Setup time, SEGEN low before SEGCLK

↑

10

ns

4

th(SEGEN)

Hold time, SEGEN low after SEGCLK

↑

1

ns

† The UTOPIA-clock (ATMCLK) frequency cannot be greater than three times the PCI-clock (PCLK) frequency or less than one-third the PCI-clock

(PCLK) frequency because synchronization can break down on the FIFOs and cells can be lost. If this relationship is maintained between the

PCLK clock and the ATMCLK clock, the PCLK clock can operate at or below 33 MHz and cells are not lost.

NOTE 7: All output signals are generated on the rising edge of SEGCLK. All inputs are sampled on the rising edge of SEGCLK.

operating characteristics (see Note 7 and Figure 18)

UTOPIA interface

NO.

PARAMETER

MIN

MAX

UNIT

5

td(SEGCLAV)

Delay time, SEGCLK

↑ to SEGCLAV↓

1

20

ns

6

td(SEGSOC)

Delay time, SEGCLK

↑ to SEGSOC↑

1

20

ns

7

td(SEGDATA)

Delay time, SEGCLK

↑ to SEGDATA7–SEGDATA0 valid

1

20

ns

8

td(SEGPAR)

Delay time, SEGCLK

↑ to SEGPAR valid

1

20

ns

NOTE 7. All output signals are generated on the rising edge of SEGCLK. All inputs are sampled on the rising edge of SEGCLK.

SEGDATA7–

SEGDATA0

(output)

SEGCLAV

(output)

SEGCLK

(input)

1

2

SEGSOC

(output)

6

7

SEGEN

(input)

Byte 1

Byte 2

Byte 3

Byte 49

Input

Ignored

Byte 50

Byte 48

Byte 51

4

5

3

SEGPAR

(output)

8

Figure 18. Segmentation-Cell Interface (PHY/ATM Low)