MFRC63002R datasheet(22/118 Pages) NXP

22 / 118 page

MFRC630

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Product data sheet

COMPANY PUBLIC

Rev. 3.1 — 6 September 2012

227531

22 of 118

NXP Semiconductors

MFRC630

Contactless reader IC

In order to support a fast FIFO data transfer, the address pointer is not incremented

automatically in case the address is pointing to the FIFO.

The read/write bit shall be set to logic 1.

8.4.4.9

I2CL-bus interface

The MFRC630 provides an interface option according to of a logical handling of an I2C

interface. This logical interface fulfills the I2C specification, but the rise/fall timings will not

be according the I2C standard. Standard I/O pads are used for communication and the

communication speed is limited to 5 MBaud. The protocol itself is equivalent to the fast

mode protocol of I2C. The address is 01010xxb, where the last two bits of the address can

be defined by the application. The definition of this bits can be done by two options. With a

pin, where the higher bit is fixed to 0 or the configuration can be defined via EEPROM.

Refer to the EEPROM configuration in Section 8.7.

Fig 17. Register read and write access

001aam305

Ack

(W)

Ack

I2C slave address

A7-A0

CLRC663 register

address A6-A0

Ack

DATA

[7..0]

[0..n]

Ack

(W)

Ack

Optional, if the previous access was on the same register address

Read Cycle

Write Cycle

I2C slave address

A7-A0

CLRC663 register

address A6-A0

(R)

Ack

sent by master

sent by slave

I2C slave address

A7-A0

Ack

DATA

[7..0]

[0..n]

0..n

Nack

DATA

[7..0]

Table 16.

Timing parameter I2CL

Parameter

Min

Max

Unit

fSCL

05MHz

tHD;STA

tLOW

100

tHIGH

100

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