MFRC63002R datasheet(18/118 Pages) NXP

18 / 118 page

MFRC630

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Product data sheet

COMPANY PUBLIC

Rev. 3.1 — 6 September 2012

227531

18 of 118

NXP Semiconductors

MFRC630

Contactless reader IC

8.4.4 I2C-bus interface

8.4.4.1

General

An Inter IC (I2C) bus interface is supported to enable a low cost, low pin count serial bus

interface to the host. The implemented I2C interface is mainly implemented according the

NXP Semiconductors I2C interface specification, rev. 3.0, June 2007. The MFRC630 can

act as a slave receiver or slave transmitter in standard mode, fast mode and fast mode

plus.

The following features defined by the NXP Semiconductors I2C interface specification,

rev. 3.0, June 2007 are not supported:

• The MFRC630 I2C interface does not stretch the clock

• The MFRC630 I2C interface does not support the general call. This means that the

MFRC630 does not support a software reset

• The MFRC630 does not support the I2C device ID

• The implemented interface can only act in slave mode. Therefore no clock generation

and access arbitration is implemented in the MFRC630.

• High speed mode is not supported by the MFRC630

SDA is a bidirectional line, connected to a positive supply voltage via a pull-up resistor.

Both lines SDA and SCL are set to HIGH level if no data is transmitted. Data on the

I2C-bus can be transferred at data rates of up to 400 kbit/s in fast mode, up to 1 Mbit/s in

the fast mode+.

If the I2C interface is selected, a spike suppression according to the I2C interface

specification on SCL and SDA is automatically activated.

For timing requirements refer to Table 194 “I2C-bus timing in fast mode and fast mode

plus”

8.4.4.2

I2C Data validity

Data on the SDA line shall be stable during the HIGH period of the clock. The HIGH state

or LOW state of the data line shall only change when the clock signal on SCL is LOW.

Fig 11. I2C-bus interface

001aam000

READER IC

SDA

SCL

PULL-UP

NETWORK

PULL-UP

NETWORK

MICROCONTROLLER

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