TMS320TCI100QGLZ datasheet(7/137 Pages) TI1

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TMS320TCI100Q

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS251E − JUNE 2004 − REVISED JUNE 2006

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

functional block and CPU (DSP core) diagram

EMIF B

Test

C64x DSP Core

Data Path B

B Register File

B31−B16

B15−B0

Instruction Fetch

Instruction Dispatch

Advanced Instruction Packet

Instruction Decode

Data Path A

A Register File

A31−A16

A15−A0

Power-Down

Logic

.L1

.S1

.M1 .D1

.D2

.M2

.S2

.L2

SDRAM

FIFO

SBSRAM

SRAM

L1P Cache

Direct-Mapped

16K Bytes Total

Control

Registers

Control

Logic

L1D Cache

2-Way Set-Associative

16K Bytes Total

Advanced

In-Circuit

Emulation

Interrupt

Control

McBSPs:

Framing Chips:

H.100, MVIP,

SCSA, T1, E1

AC97 Devices,

SPI Devices,

Codecs

C64x Digital Signal Processor

Enhanced

DMA

Controller

(64-channel)

Memory

1024K

Bytes

PLL

(x1, x6, x12,

x20)

Timer 2

EMIF A

McBSP1†

McBSP0

HPI†

ZBT SRAM

Timer 1

Timer 0

McBSP2

Boot Configuration

Interrupt

Selector

ROM/FLASH

I/O Devices

PCI†

GPIO[8:0]

UTOPIA†

GPIO[15:9]†

UTOPIA:

Up to 400 Mbps

Master ATMC

† The UTOPIA peripheral is muxed with McBSP1, and the PCI peripheral is muxed with the HPI peripheral and the GPIO[15:9] port. For

more details on the multiplexed pins of these peripherals, see the Device Configurations section of this data sheet.

VCP

TCP

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