TMS320TCI100QGLZ datasheet(33/137 Pages) TI1

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TMS320TCI100Q

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS251E − JUNE 2004 − REVISED JUNE 2006

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

signal groups description (continued)

HHWIL/PTRDY

HCNTL0/PSTOP

HCNTL1/PDEVSEL

Data

Half-Word

Select

Control

HPI†

(Host-Port Interface)

HD[31:0]/AD[31:0]

HAS/PPAR

HR/W/PCBE2

HCS/PPERR

HDS1/PSERR

HDS2/PCBE1

HRDY/PIRDY

HINT/PFRAME

(HPI16 ONLY)

† These HPI pins are muxed with the PCI peripheral. By default, these signals function as HPI. For more details on these muxed pins,

see the Device Configurations section of this data sheet.

‡ These PCI pins (excluding PCBE0 and XSP_CS) are muxed with the HPI, McBSP2, or GPIO peripherals. By default, these signals

function as HPI, McBSP2, and no function, respectively. For more details on these muxed pins, see the Device Configurations section

of this data sheet.

HD[31:0]/AD[31:0]

HR/W/PCBE2

HDS2/PCBE1

PCBE0

GP12/PGNT

GP11/PREQ

GP14/PCLK

HINT/PFRAME

GP13/PINTA

Data/Address

Arbitration

Clock

Control

PCI Interface‡

HAS/PPAR

GP15/PRST

HRDY/PIRDY

HCNTL0/PSTOP

HHWIL/PTRDY

GP10/PCBE3

GP9/PIDSEL

HCNTL1/PDEVSEL

HDS1/PSERR

Error

Command

Byte Enable

Serial

EEPROM

DX2/XSP_DO

XSP_CS

CLKX2/XSP_CLK

DR2/XSP_DI

HCS/PPERR

Figure 4. Peripheral Signals (Continued)

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