SN8P1602A datasheet(33/76 Pages) SONIX

33 / 76 page

SN8P1602B

8-Bit Micro-Controller

SONiX TECHNOLOGY CO., LTD

Page 33

Version 1.1

5 SYSTEM REGISTER

OVERVIEW

The RAM area located in 80H~FFH bank 0 is system register area. The main purpose of system registers is to control

peripheral hardware of the chip. Using system registers can control I/O ports, timers and counters by programming.

The memory map provides an easy and quick reference source for writing application program. These system registers

accessing is controlled by the selected memory bank (RBANK = 0) or the bank 0 read/write instruction (B0MOV,

B0BSET, B0BCLR…).

SYSTEM REGISTER ARRANGEMENT (BANK 0)

BYTES of SYSTEM REGISTER

SN8P1602B

PFLAG RPAGE

PUR

PEDGE

P1W

P1M

P2M

INTRQ

INTEN

OSCM

PCL

PCH

T0M

TC0M

TC0C

STKP

@YZ

STK3L STK3H STK2L STK2H STK1L STK1H STK0L STK0H

Description

PFLAG = ROM page and special flag register.

R = Working register and ROM look-up data buffer.

P1W = Port 1 wakeup register.

Y, Z = Working, @YZ and ROM addressing register.

PnM = Port n input/output mode register.

Pn = Port n data buffer.

INTRQ = Interrupt request register.

INTEN = Interrupt enable register.

OSCM = Oscillator mode register.

PCH, PCL = Program counter.

TCnM = Timer n mode register.

TCnC = Timer n counting register.

T0M.1= TC0GN, TC0 green mode wakeup flag.

STKP = Stack pointer buffer.

STK0~STK3 = Stack 0 ~ stack 3 buffer.

@YZ = RAM YZ indirect addressing index pointer.

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