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DAC5687MPZPEP bảng dữ liệu(PDF) 55 Page - Texas Instruments

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tên linh kiện DAC5687MPZPEP
Giải thích chi tiết về linh kiện  16-BIT 500-MSPS 2쨈??쨈 INTERPOLATING DUAL-CHANNEL DIGITAL-TO-ANALOG CONVERTER (DAC)
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DAC5687MPZPEP bảng dữ liệu(HTML) 55 Page - Texas Instruments

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RT
200
Ω
CLK
1:4
CLKC
Termination Resistor
Swing Limitation
Optional, May Be Bypassed
for Sine Wave Input
CAC
0.1
µF
S0029-01
Ropt
22
Ω
CLK
1:1
CLKC
Optional, Reduces
Clock Feedthrough
CAC
0.01
µF
TTL/CMOS
Source
Ropt
22
Ω
CLK
CLKC
Node CLKC Internally Biased
to CLKVDD 2
TTL/CMOS
Source
0.01
µF
S0030-01
RT
130
Ω
CAC
0.1
µF
CAC
0.1
µF
RT
130
Ω
VTT
Differential
ECL
or
(LV)PECL
Source
+
–
CLK
CLKC
RT
82.5
Ω
RT
82.5
Ω
100
Ω
S0031-01
Power Up Sequence
DAC5687-EP
SGLS333 – JUNE 2006
Figure 63. Preferred Clock Input Configuration
Figure 64. Driving the DAC5687 With a Single-Ended TTL/CMOS Clock Source
Figure 65. Driving the DAC5687 With Differential ECL/PECL Clock Source
In all conditions, bring up DVDD first. If PLLVDD is powered (PLL on), CLKVDD should be powered before or
simultaneously with PLLVDD. AVDD, CLKVDD, and IOVDD can be powered simultaneously or in any order.
Within AVDD, the multiple AVDD pins should be powered simultaneously.
55
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