DAC5687MPZPEP datasheet(34/75 Pages) TI1

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t(SCLKL)

SDENB

SCLK

SDIO

SDENB

SCLK

SDIO

Instruction Cycle

Data Transfer Cycle(s)

ts(SDENB)

t(SCLK)

th(SDIO)

ts(SDIO)

t(SCLKH)

A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

R/W

DAC5687-EP

SGLS333 – JUNE 2006

[A4 : A3 : A2 : A1 : A0] Identifies the address of the register to be accessed during the read or write operation.

For multi-byte transfers, this address is the starting address. Note that the address is written to the

DAC5687 MSB first.

Figure 34 shows the serial interface timing diagram for a DAC5687 write operation. SCLK is the serial interface

clock input to the DAC5687. Serial data enable SDENB is an active low input to the DAC5687. SDIO is serial

data in. Input data to the DAC5687 is clocked on the rising edges of SCLK.

Figure 34. Serial Interface Write Timing Diagram

Figure 35 shows the serial interface timing diagram for a DAC5687 read operation. SCLK is the serial interface

clock input to the DAC5687. Serial data enable SDENB is an active low input to the DAC5687. SDIO is serial

data in during the instruction cycle. In 3-pin configuration, SDIO is data out from the DAC5687 during the data

transfer cycle(s), while SDO is in a high-impedance state. In 4-pin configuration, SDO is data out from the

DAC5687 during the data transfer cycle(s). At the end of the data transfer, SDO outputs low on the final falling

edge of SCLK until the rising edge of SDENB when it will 3-state.

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