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DAC5687MPZPEP bảng dữ liệu(PDF) 43 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  16-BIT 500-MSPS 2쨈??쨈 INTERPOLATING DUAL-CHANNEL DIGITAL-TO-ANALOG CONVERTER (DAC)
PDF  75 Pages
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Trang chủ  http://www.ti.com
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DAC5687MPZPEP bảng dữ liệu(HTML) 43 Page - Texas Instruments

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CLK1
DA[15:0]
DB[15:0]
th(DATA)
ts(DATA)
A0
A1
A2
A3
AN
AN+1
B0
B1
B2
B3
BN
BN+1
B0053-02
CLK
Buffer
CLK
Buffer
PFD
Charge
Pump
VCO
/1
/2
/4
/8
00
01
10
11
1
0
/2
Data
Latch
1 ´2
´1
0
00
01
10
11
/2
/2
0
1
CLK1
CLK1C
CLK2
LPF
DIV[1:0]
PLLVDD
PLLLOCK
PLLVDD
D[15:0]
INTERL
SEL[1:0]
Fdac
Fdac/2 2
´
Fdac/4 ´4
Fdac/4 ´4L
Fdac/8 ´8
Data
Lock
CLK2C
DAC5687-EP
SGLS333 – JUNE 2006
Figure 46. Dual Bus Mode Timing Diagram (PLL Mode)
Figure 47. Clock Generation Architecture in PLL Mode
Power for the internal PLL blocks (PLLVDD and PLLGND) are separate from the other clock generation blocks
power (CLKVDD and CLKGND), thus minimizing PLL phase noise.
3) PLLVDD = 0 V and dual_clk = 1: DUAL CLOCK MODE
In DUAL CLOCK MODE, the DAC is driven at the DAC sample rate through CLK2/CLK2C and the input data
rate through CLK1/CLK1C. There are two options in dual clock mode: with FIFO (inv_plllock set) and without
FIFO (inv_plllock clear). If the FIFO is not used, the CLK1/CLK1C input is used to set the phase of the internal
clock divider. In this case, the edges of CLK1 and CLK2 must be aligned to within ±t_align (Figure 48), defined as
43
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