DAC5687MPZPEP datasheet(50/75 Pages) TI1

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Input Clock Synchronization of Multiple DAC5687s

CDC7005

# 1

CDC7005

# 2

DAC5687

# 1

CLK1

CLK1C

CLK2

CLK2C

DAC5687

# 2

CLK1

CLK1C

CLK2

CLK2C

DAC5687

# 3

CLK1

CLK1C

CLK2

CLK2C

DAC5687

# 4

CLK1

CLK1C

CLK2

CLK2C

Ref

INPUT

DAC

INPUT

DAC

INPUT

DAC

INPUT

DAC

INPUT

DAC

INPUT

DAC

INPUT

DAC

INPUT

DAC

Reference Operation

DAC5687-EP

SGLS333 – JUNE 2006

Table 13. Initial State of CMIX After Reset (continued)

Fix Mix Selection

phstr_del(1:0)

Initial State at PHSTR

fS4

180 degree shift

fS/4

270 degree shift

For applications where multiple DAC5687 chips are used, clock synchronization is best achieved by using

dual-clock mode with the FIFO disabled or the PLL-clock mode. In the dual-clock mode with FIFO disabled, an

appropriate clock PLL such as the CDC7005 is required to provide the DAC and input rate clocks that meet the

skew requirement t_align (see Figure 48). An example for synchronizing multiple DAC5687 devices in dual

clock mode with two CDC7005 is shown in Figure 56. When using the internal PLL-clock mode, synchronization

of multiple using PHSTR is completely deterministic due to the phase/frequency detector in the PLL feedback

loop. All chips using the same CLK1/CLK1C input clock will have identical internal clocking phases.

Figure 56. Block Diagram for Clock Synchronization of Multiple DAC5687 Devices in Dual-Clock Mode

The DAC5687 comprises a bandgap reference and control amplifier for biasing the full-scale output current. The

full-scale output current is set by applying an external resistor RBIAS to pin BIASJ. The bias current IBIAS

through resistor RBIAS is defined by the on-chip bandgap reference voltage and control amplifier. The full-scale

output current equals 16 times this bias current. The full-scale output current IOUTFS can thus be expressed as:

IOUTFS = 16 × IBIAS = 16 × VEXTIO / RBIAS

where VEXTIO is the voltage at terminal EXTIO. The bandgap reference voltage delivers an accurate voltage of

1.2 V. This reference is active when terminal EXTLO is connected to AGND. An external decoupling capacitor

CEXT of 0.1 µF should be connected externally to terminal EXTIO for compensation. The bandgap reference can

additionally be used for external reference operation. In that case, an external buffer with high impedance input

should be applied in order to limit the bandgap load current to a maximum of 100 nA. The internal reference can

be disabled and overridden by an external reference by connecting EXTLO to AVDD. Capacitor CEXT may hence

be omitted. Terminal EXTIO thus serves as either input or output node.

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