MPC5645S datasheet(115/146 Pages) FREESCALE

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Qorivva MPC5645S Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

115

The SSTL_2 differential input switch point is at vref = 0.50*vddet.

NOTE

The JEDEC SSTL_2 specifications (JESD8-9B) for a SSTL interface for class II operation

supersedes any specification in this document.

The SSTL_2 Class II output with ipp_sre[2:0] set to enabling SSTL_2 2.5V DDR1 mode,

at the destination, have a rise/fall time (10%-90%) between 1 ns and 2 ns over process,

voltage, and temperature driving a 70 ohm transmission line with 0.167 ns td terminated at

the destination with 70 ohms to Vtt (0.5*vddet) with 4.0 pf, representing the DDR input

capacitance.

Figure 31. SSTL_2 CLass II Test Load

Voh

C Output High Voltage

Level

—

vddet-0.35

—

A5.10

Vol

C Output Low Voltage

Level

——

—

0.35

A5.11

Ioh(dc)

C Output min source dc

current

Vout=Voh

-16.2

—

vddet = 2.3V

Voh = 1.95V

A5.12

Iol(dc)

C Output min sink dc

current

Vout=Vol

16.2

—

vddet = 2.3V

Vol = 0.35V

A5.13

Table 60. SSTL_2 Class II 2.5 V DDR DC Specifications (continued)

Symbol

Parameter

Condition

Min

Nom

Max

Units

Notes

SpecID

PAD

ipp_do

Z0=70 td= 0.167ns

4pF

Vtt

70 ohms

pad_st/pad_st_odt

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