MPC5645S datasheet(34/146 Pages) FREESCALE

34 / 146 page

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

2.4.6

VIU muxing

The DCU3, DCULite, and VIU2 modules share the same pins for input video. It is, however, possible to feed independent video

streams to VIU2 and DCU3 (operating in narrow mode). Figure 5 explains the pin sharing arrangement.

DDR_CAS

Column Address Strobe

Output

DDR

PCR[221]

Output,

None

DDR_RAS

Row Address Strobe

Output

DDR

PCR[227]

Output,

None

DDR_WEB

Write Enable

Output

DDR

PCR[228]

Output,

None

DDR_ODT

DRAM On-die termination

Output

DDR

PCR[226]

Output,

Pull Down

DDR_CLK

DRAM Clock

Output

DDR

PCR[225]

Output,

None

DDR_CLKB

DRAM Clock bar

Output

DDR

Output,

None

DDR_CK

DRAM Clock Enable

Output

DDR

PCR[222]

Output,

Pull Down

DDR_CS

DRAM Chip Select

Output

DDR

PCR[223]

Output,

None

MVREF

DDR Reference Voltage

Input

—

MVTT

DRAM Termination Voltage

Input

—

F2,J2,M2,R2

1 These port pins are disabled and unpowered on packages where the DRAM interface is not bonded out.

2 Reset configuration is given as I/O direction and pull direction (for example, “Input, pullup”).

Table 6. DRAM interface pin summary (continued)

Port pin1

Function

I/O

direction

Pad

type

PCR

RESET

config2

Pin number

416 TEPBGA

MPC5645S bảng dữ liệu(PDF) 34 Page - Freescale Semiconductor, Inc

MPC5645S bảng dữ liệu(HTML) 34 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL