MPC5645S datasheet(31/146 Pages) FREESCALE

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Qorivva MPC5645S Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

2.4.5

DRAM interface

The DRAM interface pins are listed in Table 6.

MDO[1]

Nexus Msg Data Out

PCR[186]

n/a

AD20

MDO[2]

Nexus Msg Data Out

PCR[187]

n/a

AE20

MDO[3]

Nexus Msg Data Out

PCR[188]

n/a

AF20

MDO[4]

Nexus Msg Data Out

PCR[189]

n/a

AE17

MDO[5]

Nexus Msg Data Out

PCR[190]

n/a

AF17

MDO[6]

Nexus Msg Data Out

PCR[191]

n/a

AC18

MDO[7]

Nexus Msg Data Out

PCR[192]

n/a

AD18

MDO[8]

Nexus Msg Data Out

PCR[193]

n/a

AE18

MDO[9]

Nexus Msg Data Out

PCR[194]

n/a

AF18

MDO[10]

Nexus Msg Data Out

PCR[195]

n/a

AC19

MDO[11]

Nexus Msg Data Out

PCR[196]

n/a

AF19

1 On the 176 LQFP and 208 LQFP package options the Nexus pins are multiplexed with other GPIO. On the 416 TEPBGA

package, there are additional dedicated Nexus pins.

Table 6. DRAM interface pin summary

Port pin1

Function

I/O

direction

Pad

type

PCR

RESET

config2

Pin number

416 TEPBGA

DRAM Data Bus

DDR_DQ[31]

DRAM Data Bus [31]

I/O

DDR

PCR[237] None, None

DDR_DQ[30]

DRAM Data Bus [30]

I/O

DDR

PCR[238] None, None

DDR_DQ[29]

DRAM Data Bus [29]

I/O

DDR

PCR[239] None, None

DDR_DQ[28]

DRAM Data Bus [28]

I/O

DDR

PCR[240] None, None

DDR_DQ[27]

DRAM Data Bus [27]

I/O

DDR

PCR[241] None, None

DDR_DQ[26]

DRAM Data Bus [26]

I/O

DDR

PCR[242] None, None

DDR_DQ[25]

DRAM Data Bus [25]

I/O

DDR

PCR[243] None, None

DDR_DQ[24]

DRAM Data Bus [24]

I/O

DDR

PCR[244] None, None

DDR_DQ[23]

DRAM Data Bus [23]

I/O

DDR

PCR[245] None, None

DDR_DQ[22]

DRAM Data Bus [22]

I/O

DDR

PCR[246] None, None

DDR_DQ[21]

DRAM Data Bus [21]

I/O

DDR

PCR[247] None, None

DDR_DQ[20]

DRAM Data Bus [20]

I/O

DDR

PCR[248] None, None

DDR_DQ[19]

DRAM Data Bus [19]

I/O

DDR

PCR[249] None, None

Table 5. Nexus pins (continued)

System pin

Function

Pad

type

PCR

Pin number1

176 LQFP

208 LQFP

416 TEPBGA

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