MPC5645S datasheet(6/146 Pages) FREESCALE

6 / 146 page

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

— Supports single, dual and quad IO serial flash memory

— Interfaces to external, memory-mapped serial flash memories

— Supports simultaneous addressing of 2 external serial flashes to achieve up 80 MB/s read bandwidth

•

RLE decoder supporting memory to memory decoding of RLE data in conjunction with eDMA

•

Four local interconnect network (LINFlex) controller modules

— Capable of autonomous message handling (master), autonomous header handling (slave mode), and UART

support

— Compliant with LIN protocol rev 2.1

•

Three controller-area network (FlexCAN) modules

— Compliant with the CAN protocol version 2.0 C

— 64 configurable buffers

— Programmable bit rate of up to 1 Mb/s

•

Four Inter-Integrated Circuit (I2C) internal bus controllers with master/slave bus interface

•

Low-power loop controlled pierce crystal oscillator supporting 4–16MHz external crystal or resonator

•

Real Time Counter (RTC) with clock source from internal 128 kHz or 16 MHz oscillator supporting autonomous

wake-up with 1 ms resolution with maximum timeout of 2 seconds

— Support for real time counter (RTC) with clock source from external 32 KHz crystal oscillator, supporting

wake-up with 1 s resolution and maximum timeout of one hour

— RTC optionally clocked by fast 4–16 MHz external oscillator

•

System timers:

— Four-channel 32-bit System Timer Module (STM)

— Eight-channel 32-bit Periodic Interrupt Timer (PIT) module (including ADC trigger)

— Software Watchdog Timer (SWT)

•

System Integration Unit Lite (SIUL) module to manage external interrupts, GPIO and pad control

•

System Status and Configuration Module (SSCM)

— Provides information for identification of the device, last boot mode, or debug status

— Provides an entry point for the censorship password mechanism

•

Clock Generation Module (MC_CGM) to generate system clock sources and provide a unified register interface,

enabling access to all clock sources

•

Clock Monitor Unit (CMU)

— Monitors the integrity of the fast (4–16 MHz) external crystal oscillator and the primary FMPLL (FMPLL0)

— Acts as a frequency meter, measuring the frequency of one clock source and comparing it to a reference clock

•

Mode Entry Module (MC_ME)

— Controls the device power mode, i.e., RUN, HALT, STOP, or STANDBY

— Controls mode transition sequences

— Manages the power control, voltage regulator, clock generation and clock management modules

•

Power Control Unit (MC_PCU) to implement standby mode entry/exit and control connections to power domains

•

Reset Generation Module (MC_RGM) to manage reset assertion and release to the device at initial power-up

•

Nexus Development Interface (NDI) per IEEE-ISTO 5001-2008 Class 3 standard with additional Class 4 features:

— Watchpoint Triggering

— Processor Overrun Control

•

Device/board boundary-scan testing supported per Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1)

•

On-chip voltage regulator controller for regulating the 3.3–5 V supply voltage down to 1.2 V for core logic (requires

external ballast transistor)

•

Package:1

— 176 LQFP, 0.5 mm pitch, 24 mm

 24 mm outline

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