MPC5645S datasheet(9/146 Pages) FREESCALE

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Qorivva MPC5645S Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

— Startup on-chip regulators in <350

s for rapid exit of STOP and STANDBY modes

— Low voltage detection on main supply and 1.2 V regulated supplies

1.4.2

e200z4d core

The e200z4d Power Architecture® core provides the following features:

•

Dual issue, 32-bit Power Architecture Book E compliant CPU

•

Implements the VLE APU for reduced code footprint

•

In-order execution and retirement

•

Precise exception handling

•

Branch processing unit

— Dedicated branch address calculation adder

— Branch target prefetching using 8-entry BTB

•

Supports independent instruction and data accesses to different memory subsystems, such as SRAM and Flash memory

via independent Instruction and Data BIUs.

•

Load/store unit

— 2 cycle load latency

— Fully pipelined

— Big and Little endian support

— Misaligned access support

•

64-bit General Purpose Register file

•

Dual AHB 2.v6 64-bit System buses

•

Memory Management Unit (MMU) with 16-entry fully-associative TLB and multiple page size support

•

4 KB, 2/4-Way Set Associative Instruction Cache

•

Signal Processing Extension (SPE1.1) APU supporting SIMD fixed-point operations using the 64-bit General Purpose

•

Embedded Floating-Point (EFP2) APU supporting scalar and vector SIMD single-precision floating-point operations,

using the 64-bit General Purpose Register file

•

Nexus Class 3 real-time Development Unit

•

Dynamic power management of execution units, cache and MMU

1.4.3

Crossbar switch (XBAR)

The XBAR multi-port crossbar switch supports simultaneous connections between seven master ports and eight slave ports.

The crossbar supports a 32-bit address bus width and a 64-bit data bus width.

The crossbar allows concurrent transactions to occur from any master port to any slave port but one of those transfers must be

an instruction fetch from internal flash. If a slave port is simultaneously requested by more than one master port, arbitration

logic selects the higher priority master and grants it ownership of the slave port. All other masters requesting that slave port are

stalled until the higher priority master completes its transactions. Requesting masters having equal priority are granted access

to a slave port in round-robin fashion, based upon the ID of the last master to be granted access.

The crossbar provides the following features:

•

Seven master ports:

— e200z4d core instruction port

— e200z4d core complex load/store data port

— eDMA controller

—DCU

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