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ADS5294IPFPR bảng dữ liệu(PDF) 27 Page - Texas Instruments

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tên linh kiện ADS5294IPFPR
Giải thích chi tiết về linh kiện  Octal Channel 14-Bit, 80 MSPS High-SNR and Low-Power ADC
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Trang chủ  http://www.ti.com
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ADS5294IPFPR bảng dữ liệu(HTML) 27 Page - Texas Instruments

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POWER SUPPLY
AVDD, LVDD
RESET
SEN
t
1
t
2
t
3
ADS5294
www.ti.com
SLAS776B – NOVEMBER 2011 – REVISED JULY 2012
RESET TIMING
Typical values at 25°C, MIN and MAX values across the full temperature range TMIN = –40°C to TMAX = 85°C (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t1
Power-on delay
Delay from power up of AVDD and LVDD to RESET pulse active
1
ms
t2
Reset pulse duration
Pulse duration of active RESET signal
50
ns
t3
Register write delay
Delay from RESET disable to CSZ active
100
ns
NOTE: A high-going pulse on RESET pin is required in serial interface mode in case of initialization through hardware reset.
For parallel interface operation, RESET has to be tied permanently HIGH.
Figure 45. Reset Timing Diagram
Copyright © 2011–2012, Texas Instruments Incorporated
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